arch/arm/mach-socfpga/misc_gen5.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <asm/io.h>
   9 #include <env.h>
  10 #include <errno.h>
  11 #include <fdtdec.h>
  12 #include <linux/libfdt.h>
  13 #include <altera.h>
  14 #include <miiphy.h>
  15 #include <netdev.h>
  16 #include <watchdog.h>
  17 #include <asm/arch/misc.h>
  18 #include <asm/arch/reset_manager.h>
  19 #include <asm/arch/scan_manager.h>
  20 #include <asm/arch/sdram.h>
  21 #include <asm/arch/system_manager.h>
  22 #include <asm/arch/nic301.h>
  23 #include <asm/arch/scu.h>
  24 #include <asm/pl310.h>
  25
  26 #include <dt-bindings/reset/altr,rst-mgr.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 static struct pl310_regs *const pl310 =
  31         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  32 static struct nic301_registers *nic301_regs =
  33         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  34 static struct scu_registers *scu_regs =
  35         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  36
  37 /*
  38  * FPGA programming support for SoC FPGA Cyclone V
  39  */
  40 static Altera_desc altera_fpga[] = {
  41         {
  42                 /* Family */
  43                 Altera_SoCFPGA,
  44                 /* Interface type */
  45                 fast_passive_parallel,
  46                 /* No limitation as additional data will be ignored */
  47                 -1,
  48                 /* No device function table */
  49                 NULL,
  50                 /* Base interface address specified in driver */
  51                 NULL,
  52                 /* No cookie implementation */
  53                 0
  54         },
  55 };
  56
  57 static const struct {
  58         const u16       pn;
  59         const char      *name;
  60         const char      *var;
  61 } socfpga_fpga_model[] = {
  62         /* Cyclone V E */
  63         { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
  64         { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
  65         { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
  66         { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
  67         { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
  68         /* Cyclone V GX/GT */
  69         { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
  70         { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
  71         { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
  72         { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
  73         { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
  74         /* Cyclone V SE/SX/ST */
  75         { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
  76         { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
  77         { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
  78         { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
  79         /* Arria V */
  80         { 0x2d03, "Arria V, D5", "av_d5" },
  81         /* Arria V ST/SX */
  82         { 0x2d13, "Arria V, ST/D3 or SX/B3", "av_st_d3" },
  83 };
  84
  85 static int socfpga_fpga_id(const bool print_id)
  86 {
  87         const u32 altera_mi = 0x6e;
  88         const u32 id = scan_mgr_get_fpga_id();
  89
  90         const u32 lsb = id & 0x00000001;
  91         const u32 mi = (id >> 1) & 0x000007ff;
  92         const u32 pn = (id >> 12) & 0x0000ffff;
  93         const u32 version = (id >> 28) & 0x0000000f;
  94         int i;
  95
  96         if ((mi != altera_mi) || (lsb != 1)) {
  97                 printf("FPGA:  Not Altera chip ID\n");
  98                 return -EINVAL;
  99         }
 100
 101         for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
 102                 if (pn == socfpga_fpga_model[i].pn)
 103                         break;
 104
 105         if (i == ARRAY_SIZE(socfpga_fpga_model)) {
 106                 printf("FPGA:  Unknown Altera chip, ID 0x%08x\n", id);
 107                 return -EINVAL;
 108         }
 109
 110         if (print_id)
 111                 printf("FPGA:  Altera %s, version 0x%01x\n",
 112                        socfpga_fpga_model[i].name, version);
 113         return i;
 114 }
 115
 116 /*
 117  * Print CPU information
 118  */
 119 #if defined(CONFIG_DISPLAY_CPUINFO)
 120 int print_cpuinfo(void)
 121 {
 122         const u32 bootinfo = readl(socfpga_get_sysmgr_addr() +
 123                                    SYSMGR_GEN5_BOOTINFO);
 124         const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
 125
 126         puts("CPU:   Altera SoCFPGA Platform\n");
 127         socfpga_fpga_id(1);
 128
 129         printf("BOOT:  %s\n", bsel_str[bsel].name);
 130         return 0;
 131 }
 132 #endif
 133
 134 #ifdef CONFIG_ARCH_MISC_INIT
 135 int arch_misc_init(void)
 136 {
 137         const u32 bsel = readl(socfpga_get_sysmgr_addr() +
 138                                SYSMGR_GEN5_BOOTINFO) & 0x7;
 139         const int fpga_id = socfpga_fpga_id(0);
 140         env_set("bootmode", bsel_str[bsel].mode);
 141         if (fpga_id >= 0)
 142                 env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
 143         return 0;
 144 }
 145 #endif
 146
 147 /*
 148  * Convert all NIC-301 AMBA slaves from secure to non-secure
 149  */
 150 static void socfpga_nic301_slave_ns(void)
 151 {
 152         writel(0x1, &nic301_regs->lwhps2fpgaregs);
 153         writel(0x1, &nic301_regs->hps2fpgaregs);
 154         writel(0x1, &nic301_regs->acp);
 155         writel(0x1, &nic301_regs->rom);
 156         writel(0x1, &nic301_regs->ocram);
 157         writel(0x1, &nic301_regs->sdrdata);
 158 }
 159
 160 void socfpga_sdram_remap_zero(void)
 161 {
 162         u32 remap;
 163
 164         socfpga_nic301_slave_ns();
 165
 166         /*
 167          * Private components security:
 168          * U-Boot : configure private timer, global timer and cpu component
 169          * access as non secure for kernel stage (as required by Linux)
 170          */
 171         setbits_le32(&scu_regs->sacr, 0xfff);
 172
 173         /* Configure the L2 controller to make SDRAM start at 0 */
 174         remap = 0x1; /* remap.mpuzero */
 175         /* Keep fpga bridge enabled when running from FPGA onchip RAM */
 176         if (socfpga_is_booting_from_fpga())
 177                 remap |= 0x8; /* remap.hps2fpga */
 178         writel(remap, &nic301_regs->remap);
 179
 180         writel(0x1, &pl310->pl310_addr_filter_start);
 181 }
 182
 183 static u32 iswgrp_handoff[8];
 184
 185 int arch_early_init_r(void)
 186 {
 187         int i;
 188
 189         /*
 190          * Write magic value into magic register to unlock support for
 191          * issuing warm reset. The ancient kernel code expects this
 192          * value to be written into the register by the bootloader, so
 193          * to support that old code, we write it here instead of in the
 194          * reset_cpu() function just before resetting the CPU.
 195          */
 196         writel(0xae9efebc,
 197                socfpga_get_sysmgr_addr() + SYSMGR_GEN5_WARMRAMGRP_EN);
 198
 199         for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
 200                 iswgrp_handoff[i] = readl(socfpga_get_sysmgr_addr() +
 201                                           SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
 202
 203         socfpga_bridges_reset(1);
 204
 205         socfpga_sdram_remap_zero();
 206
 207         /* Add device descriptor to FPGA device table */
 208         socfpga_fpga_add(&altera_fpga[0]);
 209
 210         return 0;
 211 }
 212
 213 #ifndef CONFIG_SPL_BUILD
 214 static struct socfpga_sdr_ctrl *sdr_ctrl =
 215         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
 216
 217 void do_bridge_reset(int enable, unsigned int mask)
 218 {
 219         int i;
 220
 221         if (enable) {
 222                 socfpga_bridges_set_handoff_regs(!(mask & BIT(0)),
 223                                                  !(mask & BIT(1)),
 224                                                  !(mask & BIT(2)));
 225                 for (i = 0; i < 2; i++) {       /* Reload SW setting cache */
 226                         iswgrp_handoff[i] =
 227                                 readl(socfpga_get_sysmgr_addr() +
 228                                       SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
 229                 }
 230
 231                 writel(iswgrp_handoff[2],
 232                        socfpga_get_sysmgr_addr() +
 233                        SYSMGR_GEN5_FPGAINFGRP_MODULE);
 234                 writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
 235                 writel(iswgrp_handoff[0],
 236                        socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 237                 writel(iswgrp_handoff[1], &nic301_regs->remap);
 238
 239                 writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 240                 writel(iswgrp_handoff[0],
 241                        socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 242         } else {
 243                 writel(0, socfpga_get_sysmgr_addr() +
 244                        SYSMGR_GEN5_FPGAINFGRP_MODULE);
 245                 writel(0, &sdr_ctrl->fpgaport_rst);
 246                 writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 247                 writel(1, &nic301_regs->remap);
 248         }
 249 }
 250 #endif