1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Intel Corporation
14 #include <asm/arch/misc.h>
15 #include <asm/arch/pinmux.h>
16 #include <asm/arch/reset_manager.h>
17 #include <asm/arch/reset_manager_arria10.h>
18 #include <asm/arch/sdram_arria10.h>
19 #include <asm/arch/system_manager.h>
20 #include <asm/arch/nic301.h>
22 #include <asm/pl310.h>
24 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08
25 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
26 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68
27 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18
28 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
29 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
32 * FPGA programming support for SoC FPGA Arria 10
34 static Altera_desc altera_fpga[] = {
39 fast_passive_parallel,
40 /* No limitation as additional data will be ignored */
42 /* No device function table */
44 /* Base interface address specified in driver */
46 /* No cookie implementation */
51 #if defined(CONFIG_SPL_BUILD)
52 static struct pl310_regs *const pl310 =
53 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
54 static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
55 (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
58 + * This function initializes security policies to be consistent across
59 + * all logic units in the Arria 10.
61 + * The idea is to set all security policies to be normal, nonsecure
64 void socfpga_init_security_policies(void)
66 /* Put OCRAM in non-secure */
67 writel(0x003f0000, &noc_fw_ocram_base->region0);
68 writel(0x1, &noc_fw_ocram_base->enable);
70 /* Put DDR in non-secure */
71 writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc);
72 writel(0x1, SOCFPGA_SDR_FIREWALL_L3_ADDRESS);
74 /* Enable priviledged and non-priviledged access to L4 peripherals */
75 writel(~0, SOCFPGA_NOC_L4_PRIV_FLT_OFST);
77 /* Enable secure and non-secure transactions to bridges */
78 writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST);
79 writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4);
82 socfpga_get_sysmgr_addr() + SYSMGR_A10_ECC_INTMASK_SET);
85 void socfpga_sdram_remap_zero(void)
87 /* Configure the L2 controller to make SDRAM start at 0 */
88 writel(0x1, &pl310->pl310_addr_filter_start);
92 int arch_early_init_r(void)
94 /* Add device descriptor to FPGA device table */
95 socfpga_fpga_add(&altera_fpga[0]);
101 * Print CPU information
103 #if defined(CONFIG_DISPLAY_CPUINFO)
104 int print_cpuinfo(void)
106 const u32 bootinfo = readl(socfpga_get_sysmgr_addr() +
107 SYSMGR_A10_BOOTINFO);
108 const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
110 puts("CPU: Altera SoCFPGA Arria 10\n");
112 printf("BOOT: %s\n", bsel_str[bsel].name);
117 void do_bridge_reset(int enable, unsigned int mask)
120 socfpga_reset_deassert_bridges_handoff();
122 socfpga_bridges_reset();