2 * Copyright (C) 2016-2017 Intel Corporation
4 * SPDX-License-Identifier: GPL-2.0
15 #include <asm/arch/misc.h>
16 #include <asm/arch/pinmux.h>
17 #include <asm/arch/reset_manager.h>
18 #include <asm/arch/sdram_arria10.h>
19 #include <asm/arch/system_manager.h>
20 #include <asm/arch/nic301.h>
22 #include <asm/pl310.h>
24 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08
25 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
26 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68
27 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18
28 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
29 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
31 DECLARE_GLOBAL_DATA_PTR;
33 #if defined(CONFIG_SPL_BUILD)
34 static struct pl310_regs *const pl310 =
35 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
36 static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
37 (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
40 static struct socfpga_system_manager *sysmgr_regs =
41 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
44 * DesignWare Ethernet initialization
46 #ifdef CONFIG_ETH_DESIGNWARE
47 void dwmac_deassert_reset(const unsigned int of_reset_id,
52 if (of_reset_id == EMAC0_RESET) {
53 reset = SOCFPGA_RESET(EMAC0);
54 } else if (of_reset_id == EMAC1_RESET) {
55 reset = SOCFPGA_RESET(EMAC1);
56 } else if (of_reset_id == EMAC2_RESET) {
57 reset = SOCFPGA_RESET(EMAC2);
59 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
63 clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET],
64 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
67 /* Release the EMAC controller from reset */
68 socfpga_per_reset(reset, 0);
72 #if defined(CONFIG_SPL_BUILD)
74 + * This function initializes security policies to be consistent across
75 + * all logic units in the Arria 10.
77 + * The idea is to set all security policies to be normal, nonsecure
80 static void initialize_security_policies(void)
82 /* Put OCRAM in non-secure */
83 writel(0x003f0000, &noc_fw_ocram_base->region0);
84 writel(0x1, &noc_fw_ocram_base->enable);
87 int arch_early_init_r(void)
89 initialize_security_policies();
91 /* Configure the L2 controller to make SDRAM start at 0 */
92 writel(0x1, &pl310->pl310_addr_filter_start);
94 /* assert reset to all except L4WD0 and L4TIMER0 */
95 socfpga_per_reset_all();
97 /* configuring the clock based on handoff */
98 /* TODO: Add call to cm_basic_init() */
100 /* Add device descriptor to FPGA device table */
105 int arch_early_init_r(void)
112 * This function looking the 1st encounter UART peripheral,
113 * and then return its offset of the dedicated/shared IO pin
114 * mux. offset value (zero and above).
116 static int find_peripheral_uart(const void *blob,
117 int child, const char *node_name)
120 fdt_addr_t base_addr = 0;
123 u32 value, offset = 0;
125 base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
126 if (base_addr != FDT_ADDR_T_NONE) {
127 cell = fdt_getprop(blob, child, "pinctrl-single,pins",
130 for (; len > 0; len -= (2 * sizeof(u32))) {
131 offset = fdt32_to_cpu(*cell++);
132 value = fdt32_to_cpu(*cell++);
133 /* Found UART peripheral. */
134 if (value == PINMUX_UART)
143 * This function looks up the 1st encounter UART peripheral,
144 * and then return its offset of the dedicated/shared IO pin
145 * mux. UART peripheral is found if the offset is not in negative
148 static int is_peripheral_uart_true(const void *blob,
149 int node, const char *child_name)
152 const char *node_name;
154 child = fdt_first_subnode(blob, node);
159 node_name = fdt_get_name(blob, child, &len);
162 if (!strcmp(child_name, node_name))
163 return find_peripheral_uart(blob, child, node_name);
165 child = fdt_next_subnode(blob, child);
169 node_name = fdt_get_name(blob, child, &len);
176 * This function looking the 1st encounter UART dedicated IO peripheral,
177 * and then return based address of the 1st encounter UART dedicated
180 unsigned int dedicated_uart_com_port(const void *blob)
184 node = fdtdec_next_compatible(blob, 0,
185 COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
189 if (is_peripheral_uart_true(blob, node, "dedicated") >= 0)
190 return SOCFPGA_UART1_ADDRESS;
196 * This function looking the 1st encounter UART shared IO peripheral, and then
197 * return based address of the 1st encounter UART shared IO peripheral.
199 unsigned int shared_uart_com_port(const void *blob)
203 node = fdtdec_next_compatible(blob, 0,
204 COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
208 ret = is_peripheral_uart_true(blob, node, "shared");
210 if (ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 ||
211 ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 ||
212 ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3)
213 return SOCFPGA_UART0_ADDRESS;
214 else if (ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 ||
215 ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 ||
216 ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3)
217 return SOCFPGA_UART1_ADDRESS;
223 * This function looking the 1st encounter UART peripheral, and then return
224 * base address of the 1st encounter UART peripheral.
226 unsigned int uart_com_port(const void *blob)
230 ret = dedicated_uart_com_port(blob);
235 return shared_uart_com_port(blob);
239 * Print CPU information
241 #if defined(CONFIG_DISPLAY_CPUINFO)
242 int print_cpuinfo(void)
245 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
247 puts("CPU: Altera SoCFPGA Arria 10\n");
249 printf("BOOT: %s\n", bsel_str[bsel].name);
254 #ifdef CONFIG_ARCH_MISC_INIT
255 int arch_misc_init(void)