arch/arm/mach-socfpga/misc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <errno.h>
   9 #include <fdtdec.h>
  10 #include <linux/libfdt.h>
  11 #include <altera.h>
  12 #include <miiphy.h>
  13 #include <netdev.h>
  14 #include <watchdog.h>
  15 #include <asm/arch/misc.h>
  16 #include <asm/arch/reset_manager.h>
  17 #include <asm/arch/scan_manager.h>
  18 #include <asm/arch/system_manager.h>
  19 #include <asm/arch/nic301.h>
  20 #include <asm/arch/scu.h>
  21 #include <asm/pl310.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #ifdef CONFIG_SYS_L2_PL310
  26 static const struct pl310_regs *const pl310 =
  27         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  28 #endif
  29
  30 struct bsel bsel_str[] = {
  31         { "rsvd", "Reserved", },
  32         { "fpga", "FPGA (HPS2FPGA Bridge)", },
  33         { "nand", "NAND Flash (1.8V)", },
  34         { "nand", "NAND Flash (3.0V)", },
  35         { "sd", "SD/MMC External Transceiver (1.8V)", },
  36         { "sd", "SD/MMC Internal Transceiver (3.0V)", },
  37         { "qspi", "QSPI Flash (1.8V)", },
  38         { "qspi", "QSPI Flash (3.0V)", },
  39 };
  40
  41 int dram_init(void)
  42 {
  43         if (fdtdec_setup_mem_size_base() != 0)
  44                 return -EINVAL;
  45
  46         return 0;
  47 }
  48
  49 void enable_caches(void)
  50 {
  51 #ifndef CONFIG_SYS_ICACHE_OFF
  52         icache_enable();
  53 #endif
  54 #ifndef CONFIG_SYS_DCACHE_OFF
  55         dcache_enable();
  56 #endif
  57 }
  58
  59 #ifdef CONFIG_SYS_L2_PL310
  60 void v7_outer_cache_enable(void)
  61 {
  62         /* Disable the L2 cache */
  63         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  64
  65         writel(0x111, &pl310->pl310_tag_latency_ctrl);
  66         writel(0x121, &pl310->pl310_data_latency_ctrl);
  67
  68         /* enable BRESP, instruction and data prefetch, full line of zeroes */
  69         setbits_le32(&pl310->pl310_aux_ctrl,
  70                      L310_AUX_CTRL_DATA_PREFETCH_MASK |
  71                      L310_AUX_CTRL_INST_PREFETCH_MASK |
  72                      L310_SHARED_ATT_OVERRIDE_ENABLE);
  73
  74         /* Enable the L2 cache */
  75         setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  76 }
  77
  78 void v7_outer_cache_disable(void)
  79 {
  80         /* Disable the L2 cache */
  81         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  82 }
  83 #endif
  84
  85 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
  86 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
  87 int overwrite_console(void)
  88 {
  89         return 0;
  90 }
  91 #endif
  92
  93 #ifdef CONFIG_FPGA
  94 /* add device descriptor to FPGA device table */
  95 void socfpga_fpga_add(void *fpga_desc)
  96 {
  97         fpga_init();
  98         fpga_add(fpga_altera, fpga_desc);
  99 }
 100 #endif
 101
 102 int arch_cpu_init(void)
 103 {
 104 #ifdef CONFIG_HW_WATCHDOG
 105         /*
 106          * In case the watchdog is enabled, make sure to (re-)configure it
 107          * so that the defined timeout is valid. Otherwise the SPL (Perloader)
 108          * timeout value is still active which might too short for Linux
 109          * booting.
 110          */
 111         hw_watchdog_init();
 112 #else
 113         /*
 114          * If the HW watchdog is NOT enabled, make sure it is not running,
 115          * for example because it was enabled in the preloader. This might
 116          * trigger a watchdog-triggered reboot of Linux kernel later.
 117          * Toggle watchdog reset, so watchdog in not running state.
 118          */
 119         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 120         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 121 #endif
 122
 123         return 0;
 124 }
 125
 126 #ifndef CONFIG_SPL_BUILD
 127 static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 128 {
 129         if (argc != 2)
 130                 return CMD_RET_USAGE;
 131
 132         argv++;
 133
 134         switch (*argv[0]) {
 135         case 'e':       /* Enable */
 136                 do_bridge_reset(1);
 137                 break;
 138         case 'd':       /* Disable */
 139                 do_bridge_reset(0);
 140                 break;
 141         default:
 142                 return CMD_RET_USAGE;
 143         }
 144
 145         return 0;
 146 }
 147
 148 U_BOOT_CMD(bridge, 2, 1, do_bridge,
 149            "SoCFPGA HPS FPGA bridge control",
 150            "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 151            "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 152            ""
 153 );
 154
 155 #endif