1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
10 #include <linux/libfdt.h>
15 #include <asm/arch/misc.h>
16 #include <asm/arch/reset_manager.h>
17 #include <asm/arch/scan_manager.h>
18 #include <asm/arch/system_manager.h>
19 #include <asm/arch/nic301.h>
20 #include <asm/arch/scu.h>
21 #include <asm/pl310.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #ifdef CONFIG_SYS_L2_PL310
26 static const struct pl310_regs *const pl310 =
27 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
30 struct bsel bsel_str[] = {
31 { "rsvd", "Reserved", },
32 { "fpga", "FPGA (HPS2FPGA Bridge)", },
33 { "nand", "NAND Flash (1.8V)", },
34 { "nand", "NAND Flash (3.0V)", },
35 { "sd", "SD/MMC External Transceiver (1.8V)", },
36 { "sd", "SD/MMC Internal Transceiver (3.0V)", },
37 { "qspi", "QSPI Flash (1.8V)", },
38 { "qspi", "QSPI Flash (3.0V)", },
43 if (fdtdec_setup_mem_size_base() != 0)
49 void enable_caches(void)
51 #ifndef CONFIG_SYS_ICACHE_OFF
54 #ifndef CONFIG_SYS_DCACHE_OFF
59 #ifdef CONFIG_SYS_L2_PL310
60 void v7_outer_cache_enable(void)
62 /* Disable the L2 cache */
63 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
65 writel(0x0, &pl310->pl310_tag_latency_ctrl);
66 writel(0x10, &pl310->pl310_data_latency_ctrl);
68 /* enable BRESP, instruction and data prefetch, full line of zeroes */
69 setbits_le32(&pl310->pl310_aux_ctrl,
70 L310_AUX_CTRL_DATA_PREFETCH_MASK |
71 L310_AUX_CTRL_INST_PREFETCH_MASK |
72 L310_SHARED_ATT_OVERRIDE_ENABLE);
74 /* Enable the L2 cache */
75 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
78 void v7_outer_cache_disable(void)
80 /* Disable the L2 cache */
81 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
85 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
86 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
87 int overwrite_console(void)
94 /* add device descriptor to FPGA device table */
95 void socfpga_fpga_add(void *fpga_desc)
98 fpga_add(fpga_altera, fpga_desc);
102 int arch_cpu_init(void)
104 #ifdef CONFIG_HW_WATCHDOG
106 * In case the watchdog is enabled, make sure to (re-)configure it
107 * so that the defined timeout is valid. Otherwise the SPL (Perloader)
108 * timeout value is still active which might too short for Linux
114 * If the HW watchdog is NOT enabled, make sure it is not running,
115 * for example because it was enabled in the preloader. This might
116 * trigger a watchdog-triggered reboot of Linux kernel later.
117 * Toggle watchdog reset, so watchdog in not running state.
119 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
120 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
126 #ifndef CONFIG_SPL_BUILD
127 static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
130 return CMD_RET_USAGE;
135 case 'e': /* Enable */
138 case 'd': /* Disable */
142 return CMD_RET_USAGE;
148 U_BOOT_CMD(bridge, 2, 1, do_bridge,
149 "SoCFPGA HPS FPGA bridge control",
150 "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
151 "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"