arch/arm/mach-socfpga/misc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <asm/io.h>
   9 #include <errno.h>
  10 #include <fdtdec.h>
  11 #include <linux/libfdt.h>
  12 #include <altera.h>
  13 #include <miiphy.h>
  14 #include <netdev.h>
  15 #include <watchdog.h>
  16 #include <asm/arch/misc.h>
  17 #include <asm/arch/reset_manager.h>
  18 #include <asm/arch/scan_manager.h>
  19 #include <asm/arch/system_manager.h>
  20 #include <asm/arch/nic301.h>
  21 #include <asm/arch/scu.h>
  22 #include <asm/pl310.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 phys_addr_t socfpga_clkmgr_base __section(".data");
  27 phys_addr_t socfpga_rstmgr_base __section(".data");
  28 phys_addr_t socfpga_sysmgr_base __section(".data");
  29
  30 #ifdef CONFIG_SYS_L2_PL310
  31 static const struct pl310_regs *const pl310 =
  32         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  33 #endif
  34
  35 struct bsel bsel_str[] = {
  36         { "rsvd", "Reserved", },
  37         { "fpga", "FPGA (HPS2FPGA Bridge)", },
  38         { "nand", "NAND Flash (1.8V)", },
  39         { "nand", "NAND Flash (3.0V)", },
  40         { "sd", "SD/MMC External Transceiver (1.8V)", },
  41         { "sd", "SD/MMC Internal Transceiver (3.0V)", },
  42         { "qspi", "QSPI Flash (1.8V)", },
  43         { "qspi", "QSPI Flash (3.0V)", },
  44 };
  45
  46 int dram_init(void)
  47 {
  48         if (fdtdec_setup_mem_size_base() != 0)
  49                 return -EINVAL;
  50
  51         return 0;
  52 }
  53
  54 void enable_caches(void)
  55 {
  56 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  57         icache_enable();
  58 #endif
  59 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  60         dcache_enable();
  61 #endif
  62 }
  63
  64 #ifdef CONFIG_SYS_L2_PL310
  65 void v7_outer_cache_enable(void)
  66 {
  67         struct udevice *dev;
  68
  69         if (uclass_get_device(UCLASS_CACHE, 0, &dev))
  70                 pr_err("cache controller driver NOT found!\n");
  71 }
  72
  73 void v7_outer_cache_disable(void)
  74 {
  75         /* Disable the L2 cache */
  76         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  77 }
  78
  79 void socfpga_pl310_clear(void)
  80 {
  81         u32 mask = 0xff, ena = 0;
  82
  83         icache_enable();
  84
  85         /* Disable the L2 cache */
  86         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  87
  88         writel(0x0, &pl310->pl310_tag_latency_ctrl);
  89         writel(0x10, &pl310->pl310_data_latency_ctrl);
  90
  91         /* enable BRESP, instruction and data prefetch, full line of zeroes */
  92         setbits_le32(&pl310->pl310_aux_ctrl,
  93                      L310_AUX_CTRL_DATA_PREFETCH_MASK |
  94                      L310_AUX_CTRL_INST_PREFETCH_MASK |
  95                      L310_SHARED_ATT_OVERRIDE_ENABLE);
  96
  97         /* Enable the L2 cache */
  98         ena = readl(&pl310->pl310_ctrl);
  99         ena |= L2X0_CTRL_EN;
 100
 101         /*
 102          * Invalidate the PL310 L2 cache. Keep the invalidation code
 103          * entirely in L1 I-cache to avoid any bus traffic through
 104          * the L2.
 105          */
 106         asm volatile(
 107                 ".align 5                       \n"
 108                 "       b       3f              \n"
 109                 "1:     str     %1,     [%4]    \n"
 110                 "       dsb                     \n"
 111                 "       isb                     \n"
 112                 "       str     %0,     [%2]    \n"
 113                 "       dsb                     \n"
 114                 "       isb                     \n"
 115                 "2:     ldr     %0,     [%2]    \n"
 116                 "       cmp     %0,     #0      \n"
 117                 "       bne     2b              \n"
 118                 "       str     %0,     [%3]    \n"
 119                 "       dsb                     \n"
 120                 "       isb                     \n"
 121                 "       b       4f              \n"
 122                 "3:     b       1b              \n"
 123                 "4:     nop                     \n"
 124         : "+r"(mask), "+r"(ena)
 125         : "r"(&pl310->pl310_inv_way),
 126           "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
 127         : "memory", "cc");
 128
 129         /* Disable the L2 cache */
 130         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 131 }
 132 #endif
 133
 134 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 135 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 136 int overwrite_console(void)
 137 {
 138         return 0;
 139 }
 140 #endif
 141
 142 #ifdef CONFIG_FPGA
 143 /* add device descriptor to FPGA device table */
 144 void socfpga_fpga_add(void *fpga_desc)
 145 {
 146         fpga_init();
 147         fpga_add(fpga_altera, fpga_desc);
 148 }
 149 #endif
 150
 151 int arch_cpu_init(void)
 152 {
 153         socfpga_get_managers_addr();
 154
 155 #ifdef CONFIG_HW_WATCHDOG
 156         /*
 157          * In case the watchdog is enabled, make sure to (re-)configure it
 158          * so that the defined timeout is valid. Otherwise the SPL (Perloader)
 159          * timeout value is still active which might too short for Linux
 160          * booting.
 161          */
 162         hw_watchdog_init();
 163 #else
 164         /*
 165          * If the HW watchdog is NOT enabled, make sure it is not running,
 166          * for example because it was enabled in the preloader. This might
 167          * trigger a watchdog-triggered reboot of Linux kernel later.
 168          * Toggle watchdog reset, so watchdog in not running state.
 169          */
 170         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 171         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 172 #endif
 173
 174         return 0;
 175 }
 176
 177 #ifndef CONFIG_SPL_BUILD
 178 static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 179 {
 180         unsigned int mask = ~0;
 181
 182         if (argc < 2 || argc > 3)
 183                 return CMD_RET_USAGE;
 184
 185         argv++;
 186
 187         if (argc == 3)
 188                 mask = simple_strtoul(argv[1], NULL, 16);
 189
 190         switch (*argv[0]) {
 191         case 'e':       /* Enable */
 192                 do_bridge_reset(1, mask);
 193                 break;
 194         case 'd':       /* Disable */
 195                 do_bridge_reset(0, mask);
 196                 break;
 197         default:
 198                 return CMD_RET_USAGE;
 199         }
 200
 201         return 0;
 202 }
 203
 204 U_BOOT_CMD(bridge, 3, 1, do_bridge,
 205            "SoCFPGA HPS FPGA bridge control",
 206            "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 207            "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 208            ""
 209 );
 210
 211 #endif
 212
 213 static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
 214 {
 215         const void *blob = gd->fdt_blob;
 216         struct fdt_resource r;
 217         int node;
 218         int ret;
 219
 220         node = fdt_node_offset_by_compatible(blob, -1, compat);
 221         if (node < 0)
 222                 return node;
 223
 224         if (!fdtdec_get_is_enabled(blob, node))
 225                 return -ENODEV;
 226
 227         ret = fdt_get_resource(blob, node, "reg", 0, &r);
 228         if (ret)
 229                 return ret;
 230
 231         *base = (phys_addr_t)r.start;
 232
 233         return 0;
 234 }
 235
 236 void socfpga_get_managers_addr(void)
 237 {
 238         int ret;
 239
 240         ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
 241         if (ret)
 242                 hang();
 243
 244         ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
 245         if (ret)
 246                 hang();
 247
 248 #ifdef CONFIG_TARGET_SOCFPGA_AGILEX
 249         ret = socfpga_get_base_addr("intel,agilex-clkmgr",
 250                                     &socfpga_clkmgr_base);
 251 #else
 252         ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
 253 #endif
 254         if (ret)
 255                 hang();
 256 }
 257
 258 phys_addr_t socfpga_get_rstmgr_addr(void)
 259 {
 260         return socfpga_rstmgr_base;
 261 }
 262
 263 phys_addr_t socfpga_get_sysmgr_addr(void)
 264 {
 265         return socfpga_sysmgr_base;
 266 }
 267
 268 phys_addr_t socfpga_get_clkmgr_addr(void)
 269 {
 270         return socfpga_clkmgr_base;
 271 }