arch/arm/mach-socfpga/misc.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <errno.h>
  10 #include <fdtdec.h>
  11 #include <libfdt.h>
  12 #include <altera.h>
  13 #include <miiphy.h>
  14 #include <netdev.h>
  15 #include <watchdog.h>
  16 #include <asm/arch/reset_manager.h>
  17 #include <asm/arch/scan_manager.h>
  18 #include <asm/arch/system_manager.h>
  19 #include <asm/arch/dwmmc.h>
  20 #include <asm/arch/nic301.h>
  21 #include <asm/arch/scu.h>
  22 #include <asm/pl310.h>
  23
  24 #include <dt-bindings/reset/altr,rst-mgr.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 static struct pl310_regs *const pl310 =
  29         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  30 static struct socfpga_system_manager *sysmgr_regs =
  31         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  32 static struct socfpga_reset_manager *reset_manager_base =
  33         (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
  34 static struct nic301_registers *nic301_regs =
  35         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  36 static struct scu_registers *scu_regs =
  37         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  38
  39 int dram_init(void)
  40 {
  41         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  42         return 0;
  43 }
  44
  45 void enable_caches(void)
  46 {
  47 #ifndef CONFIG_SYS_ICACHE_OFF
  48         icache_enable();
  49 #endif
  50 #ifndef CONFIG_SYS_DCACHE_OFF
  51         dcache_enable();
  52 #endif
  53 }
  54
  55 void v7_outer_cache_enable(void)
  56 {
  57         /* disable the L2 cache */
  58         writel(0, &pl310->pl310_ctrl);
  59
  60         /* enable BRESP, instruction and data prefetch, full line of zeroes */
  61         setbits_le32(&pl310->pl310_aux_ctrl,
  62                      L310_AUX_CTRL_DATA_PREFETCH_MASK |
  63                      L310_AUX_CTRL_INST_PREFETCH_MASK |
  64                      L310_SHARED_ATT_OVERRIDE_ENABLE);
  65 }
  66
  67 /*
  68  * DesignWare Ethernet initialization
  69  */
  70 #ifdef CONFIG_ETH_DESIGNWARE
  71 static void dwmac_deassert_reset(const unsigned int of_reset_id)
  72 {
  73         u32 physhift, reset;
  74
  75         if (of_reset_id == EMAC0_RESET) {
  76                 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
  77                 reset = SOCFPGA_RESET(EMAC0);
  78         } else if (of_reset_id == EMAC1_RESET) {
  79                 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
  80                 reset = SOCFPGA_RESET(EMAC1);
  81         } else {
  82                 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
  83                 return;
  84         }
  85
  86         /* Clearing emac0 PHY interface select to 0 */
  87         clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
  88                      SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
  89
  90         /* configure to PHY interface select choosed */
  91         setbits_le32(&sysmgr_regs->emacgrp_ctrl,
  92                      SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
  93
  94         /* Release the EMAC controller from reset */
  95         socfpga_per_reset(reset, 0);
  96 }
  97
  98 int cpu_eth_init(bd_t *bis)
  99 {
 100         const void *fdt = gd->fdt_blob;
 101         struct fdtdec_phandle_args args;
 102         int nodes[2];   /* Max. two GMACs */
 103         int ret, count;
 104         int i, node;
 105
 106         /* Put both GMACs into RESET state. */
 107         socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
 108         socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
 109
 110         count = fdtdec_find_aliases_for_id(fdt, "ethernet",
 111                                            COMPAT_ALTERA_SOCFPGA_DWMAC,
 112                                            nodes, ARRAY_SIZE(nodes));
 113         for (i = 0; i < count; i++) {
 114                 node = nodes[i];
 115                 if (node <= 0)
 116                         continue;
 117
 118                 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
 119                                                      "#reset-cells", 1, 0,
 120                                                      &args);
 121                 if (ret || (args.args_count != 1)) {
 122                         debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
 123                         continue;
 124                 }
 125
 126                 dwmac_deassert_reset(args.args[0]);
 127         }
 128
 129         return 0;
 130 }
 131 #endif
 132
 133 struct {
 134         const char      *mode;
 135         const char      *name;
 136 } bsel_str[] = {
 137         { "rsvd", "Reserved", },
 138         { "fpga", "FPGA (HPS2FPGA Bridge)", },
 139         { "nand", "NAND Flash (1.8V)", },
 140         { "nand", "NAND Flash (3.0V)", },
 141         { "sd", "SD/MMC External Transceiver (1.8V)", },
 142         { "sd", "SD/MMC Internal Transceiver (3.0V)", },
 143         { "qspi", "QSPI Flash (1.8V)", },
 144         { "qspi", "QSPI Flash (3.0V)", },
 145 };
 146
 147 static const struct {
 148         const u16       pn;
 149         const char      *name;
 150         const char      *var;
 151 } const socfpga_fpga_model[] = {
 152         /* Cyclone V E */
 153         { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
 154         { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
 155         { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
 156         { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
 157         { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
 158         /* Cyclone V GX/GT */
 159         { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
 160         { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
 161         { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
 162         { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
 163         { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
 164         /* Cyclone V SE/SX/ST */
 165         { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
 166         { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
 167         { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
 168         { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
 169         /* Arria V */
 170         { 0x2d03, "Arria V, D5", "av_d5" },
 171 };
 172
 173 static int socfpga_fpga_id(const bool print_id)
 174 {
 175         const u32 altera_mi = 0x6e;
 176         const u32 id = scan_mgr_get_fpga_id();
 177
 178         const u32 lsb = id & 0x00000001;
 179         const u32 mi = (id >> 1) & 0x000007ff;
 180         const u32 pn = (id >> 12) & 0x0000ffff;
 181         const u32 version = (id >> 28) & 0x0000000f;
 182         int i;
 183
 184         if ((mi != altera_mi) || (lsb != 1)) {
 185                 printf("FPGA:  Not Altera chip ID\n");
 186                 return -EINVAL;
 187         }
 188
 189         for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
 190                 if (pn == socfpga_fpga_model[i].pn)
 191                         break;
 192
 193         if (i == ARRAY_SIZE(socfpga_fpga_model)) {
 194                 printf("FPGA:  Unknown Altera chip, ID 0x%08x\n", id);
 195                 return -EINVAL;
 196         }
 197
 198         if (print_id)
 199                 printf("FPGA:  Altera %s, version 0x%01x\n",
 200                        socfpga_fpga_model[i].name, version);
 201         return i;
 202 }
 203
 204 /*
 205  * Print CPU information
 206  */
 207 #if defined(CONFIG_DISPLAY_CPUINFO)
 208 int print_cpuinfo(void)
 209 {
 210         const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
 211         puts("CPU:   Altera SoCFPGA Platform\n");
 212         socfpga_fpga_id(1);
 213         printf("BOOT:  %s\n", bsel_str[bsel].name);
 214         return 0;
 215 }
 216 #endif
 217
 218 #ifdef CONFIG_ARCH_MISC_INIT
 219 int arch_misc_init(void)
 220 {
 221         const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
 222         const int fpga_id = socfpga_fpga_id(0);
 223         setenv("bootmode", bsel_str[bsel].mode);
 224         if (fpga_id >= 0)
 225                 setenv("fpgatype", socfpga_fpga_model[fpga_id].var);
 226         return 0;
 227 }
 228 #endif
 229
 230 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 231 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 232 int overwrite_console(void)
 233 {
 234         return 0;
 235 }
 236 #endif
 237
 238 #ifdef CONFIG_FPGA
 239 /*
 240  * FPGA programming support for SoC FPGA Cyclone V
 241  */
 242 static Altera_desc altera_fpga[] = {
 243         {
 244                 /* Family */
 245                 Altera_SoCFPGA,
 246                 /* Interface type */
 247                 fast_passive_parallel,
 248                 /* No limitation as additional data will be ignored */
 249                 -1,
 250                 /* No device function table */
 251                 NULL,
 252                 /* Base interface address specified in driver */
 253                 NULL,
 254                 /* No cookie implementation */
 255                 0
 256         },
 257 };
 258
 259 /* add device descriptor to FPGA device table */
 260 static void socfpga_fpga_add(void)
 261 {
 262         int i;
 263         fpga_init();
 264         for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
 265                 fpga_add(fpga_altera, &altera_fpga[i]);
 266 }
 267 #else
 268 static inline void socfpga_fpga_add(void) {}
 269 #endif
 270
 271 int arch_cpu_init(void)
 272 {
 273 #ifdef CONFIG_HW_WATCHDOG
 274         /*
 275          * In case the watchdog is enabled, make sure to (re-)configure it
 276          * so that the defined timeout is valid. Otherwise the SPL (Perloader)
 277          * timeout value is still active which might too short for Linux
 278          * booting.
 279          */
 280         hw_watchdog_init();
 281 #else
 282         /*
 283          * If the HW watchdog is NOT enabled, make sure it is not running,
 284          * for example because it was enabled in the preloader. This might
 285          * trigger a watchdog-triggered reboot of Linux kernel later.
 286          * Toggle watchdog reset, so watchdog in not running state.
 287          */
 288         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 289         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 290 #endif
 291
 292         return 0;
 293 }
 294
 295 /*
 296  * Convert all NIC-301 AMBA slaves from secure to non-secure
 297  */
 298 static void socfpga_nic301_slave_ns(void)
 299 {
 300         writel(0x1, &nic301_regs->lwhps2fpgaregs);
 301         writel(0x1, &nic301_regs->hps2fpgaregs);
 302         writel(0x1, &nic301_regs->acp);
 303         writel(0x1, &nic301_regs->rom);
 304         writel(0x1, &nic301_regs->ocram);
 305         writel(0x1, &nic301_regs->sdrdata);
 306 }
 307
 308 static uint32_t iswgrp_handoff[8];
 309
 310 int arch_early_init_r(void)
 311 {
 312         int i;
 313
 314         /*
 315          * Write magic value into magic register to unlock support for
 316          * issuing warm reset. The ancient kernel code expects this
 317          * value to be written into the register by the bootloader, so
 318          * to support that old code, we write it here instead of in the
 319          * reset_cpu() function just before reseting the CPU.
 320          */
 321         writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
 322
 323         for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
 324                 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
 325
 326         socfpga_bridges_reset(1);
 327         socfpga_nic301_slave_ns();
 328
 329         /*
 330          * Private components security:
 331          * U-Boot : configure private timer, global timer and cpu component
 332          * access as non secure for kernel stage (as required by Linux)
 333          */
 334         setbits_le32(&scu_regs->sacr, 0xfff);
 335
 336         /* Configure the L2 controller to make SDRAM start at 0 */
 337 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 338         writel(0x2, &nic301_regs->remap);
 339 #else
 340         writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
 341         writel(0x1, &pl310->pl310_addr_filter_start);
 342 #endif
 343
 344         /* Add device descriptor to FPGA device table */
 345         socfpga_fpga_add();
 346
 347 #ifdef CONFIG_DESIGNWARE_SPI
 348         /* Get Designware SPI controller out of reset */
 349         socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
 350         socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
 351 #endif
 352
 353         return 0;
 354 }
 355
 356 static void socfpga_sdram_apply_static_cfg(void)
 357 {
 358         const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
 359         const uint32_t applymask = 0x8;
 360         uint32_t val = readl(staticcfg) | applymask;
 361
 362         /*
 363          * SDRAM staticcfg register specific:
 364          * When applying the register setting, the CPU must not access
 365          * SDRAM. Luckily for us, we can abuse i-cache here to help us
 366          * circumvent the SDRAM access issue. The idea is to make sure
 367          * that the code is in one full i-cache line by branching past
 368          * it and back. Once it is in the i-cache, we execute the core
 369          * of the code and apply the register settings.
 370          *
 371          * The code below uses 7 instructions, while the Cortex-A9 has
 372          * 32-byte cachelines, thus the limit is 8 instructions total.
 373          */
 374         asm volatile(
 375                 ".align 5                       \n"
 376                 "       b       2f              \n"
 377                 "1:     str     %0,     [%1]    \n"
 378                 "       dsb                     \n"
 379                 "       isb                     \n"
 380                 "       b       3f              \n"
 381                 "2:     b       1b              \n"
 382                 "3:     nop                     \n"
 383         : : "r"(val), "r"(staticcfg) : "memory", "cc");
 384 }
 385
 386 int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 387 {
 388         if (argc != 2)
 389                 return CMD_RET_USAGE;
 390
 391         argv++;
 392
 393         switch (*argv[0]) {
 394         case 'e':       /* Enable */
 395                 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
 396                 socfpga_sdram_apply_static_cfg();
 397                 writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
 398                 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
 399                 writel(iswgrp_handoff[1], &nic301_regs->remap);
 400                 break;
 401         case 'd':       /* Disable */
 402                 writel(0, &sysmgr_regs->fpgaintfgrp_module);
 403                 writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
 404                 socfpga_sdram_apply_static_cfg();
 405                 writel(0, &reset_manager_base->brg_mod_reset);
 406                 writel(1, &nic301_regs->remap);
 407                 break;
 408         default:
 409                 return CMD_RET_USAGE;
 410         }
 411
 412         return 0;
 413 }
 414
 415 U_BOOT_CMD(
 416         bridge, 2, 1, do_bridge,
 417         "SoCFPGA HPS FPGA bridge control",
 418         "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 419         "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 420         ""
 421 );