arch/arm/mach-socfpga/misc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <asm/io.h>
   9 #include <errno.h>
  10 #include <fdtdec.h>
  11 #include <linux/libfdt.h>
  12 #include <altera.h>
  13 #include <miiphy.h>
  14 #include <netdev.h>
  15 #include <watchdog.h>
  16 #include <asm/arch/misc.h>
  17 #include <asm/arch/reset_manager.h>
  18 #include <asm/arch/scan_manager.h>
  19 #include <asm/arch/system_manager.h>
  20 #include <asm/arch/nic301.h>
  21 #include <asm/arch/scu.h>
  22 #include <asm/pl310.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 phys_addr_t socfpga_rstmgr_base __section(".data");
  27
  28 #ifdef CONFIG_SYS_L2_PL310
  29 static const struct pl310_regs *const pl310 =
  30         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  31 #endif
  32
  33 struct bsel bsel_str[] = {
  34         { "rsvd", "Reserved", },
  35         { "fpga", "FPGA (HPS2FPGA Bridge)", },
  36         { "nand", "NAND Flash (1.8V)", },
  37         { "nand", "NAND Flash (3.0V)", },
  38         { "sd", "SD/MMC External Transceiver (1.8V)", },
  39         { "sd", "SD/MMC Internal Transceiver (3.0V)", },
  40         { "qspi", "QSPI Flash (1.8V)", },
  41         { "qspi", "QSPI Flash (3.0V)", },
  42 };
  43
  44 int dram_init(void)
  45 {
  46         if (fdtdec_setup_mem_size_base() != 0)
  47                 return -EINVAL;
  48
  49         return 0;
  50 }
  51
  52 void enable_caches(void)
  53 {
  54 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  55         icache_enable();
  56 #endif
  57 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  58         dcache_enable();
  59 #endif
  60 }
  61
  62 #ifdef CONFIG_SYS_L2_PL310
  63 void v7_outer_cache_enable(void)
  64 {
  65         struct udevice *dev;
  66
  67         if (uclass_get_device(UCLASS_CACHE, 0, &dev))
  68                 pr_err("cache controller driver NOT found!\n");
  69 }
  70
  71 void v7_outer_cache_disable(void)
  72 {
  73         /* Disable the L2 cache */
  74         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  75 }
  76
  77 void socfpga_pl310_clear(void)
  78 {
  79         u32 mask = 0xff, ena = 0;
  80
  81         icache_enable();
  82
  83         /* Disable the L2 cache */
  84         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  85
  86         writel(0x0, &pl310->pl310_tag_latency_ctrl);
  87         writel(0x10, &pl310->pl310_data_latency_ctrl);
  88
  89         /* enable BRESP, instruction and data prefetch, full line of zeroes */
  90         setbits_le32(&pl310->pl310_aux_ctrl,
  91                      L310_AUX_CTRL_DATA_PREFETCH_MASK |
  92                      L310_AUX_CTRL_INST_PREFETCH_MASK |
  93                      L310_SHARED_ATT_OVERRIDE_ENABLE);
  94
  95         /* Enable the L2 cache */
  96         ena = readl(&pl310->pl310_ctrl);
  97         ena |= L2X0_CTRL_EN;
  98
  99         /*
 100          * Invalidate the PL310 L2 cache. Keep the invalidation code
 101          * entirely in L1 I-cache to avoid any bus traffic through
 102          * the L2.
 103          */
 104         asm volatile(
 105                 ".align 5                       \n"
 106                 "       b       3f              \n"
 107                 "1:     str     %1,     [%4]    \n"
 108                 "       dsb                     \n"
 109                 "       isb                     \n"
 110                 "       str     %0,     [%2]    \n"
 111                 "       dsb                     \n"
 112                 "       isb                     \n"
 113                 "2:     ldr     %0,     [%2]    \n"
 114                 "       cmp     %0,     #0      \n"
 115                 "       bne     2b              \n"
 116                 "       str     %0,     [%3]    \n"
 117                 "       dsb                     \n"
 118                 "       isb                     \n"
 119                 "       b       4f              \n"
 120                 "3:     b       1b              \n"
 121                 "4:     nop                     \n"
 122         : "+r"(mask), "+r"(ena)
 123         : "r"(&pl310->pl310_inv_way),
 124           "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
 125         : "memory", "cc");
 126
 127         /* Disable the L2 cache */
 128         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 129 }
 130 #endif
 131
 132 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 133 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 134 int overwrite_console(void)
 135 {
 136         return 0;
 137 }
 138 #endif
 139
 140 #ifdef CONFIG_FPGA
 141 /* add device descriptor to FPGA device table */
 142 void socfpga_fpga_add(void *fpga_desc)
 143 {
 144         fpga_init();
 145         fpga_add(fpga_altera, fpga_desc);
 146 }
 147 #endif
 148
 149 int arch_cpu_init(void)
 150 {
 151         socfpga_get_managers_addr();
 152
 153 #ifdef CONFIG_HW_WATCHDOG
 154         /*
 155          * In case the watchdog is enabled, make sure to (re-)configure it
 156          * so that the defined timeout is valid. Otherwise the SPL (Perloader)
 157          * timeout value is still active which might too short for Linux
 158          * booting.
 159          */
 160         hw_watchdog_init();
 161 #else
 162         /*
 163          * If the HW watchdog is NOT enabled, make sure it is not running,
 164          * for example because it was enabled in the preloader. This might
 165          * trigger a watchdog-triggered reboot of Linux kernel later.
 166          * Toggle watchdog reset, so watchdog in not running state.
 167          */
 168         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 169         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 170 #endif
 171
 172         return 0;
 173 }
 174
 175 #ifndef CONFIG_SPL_BUILD
 176 static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 177 {
 178         unsigned int mask = ~0;
 179
 180         if (argc < 2 || argc > 3)
 181                 return CMD_RET_USAGE;
 182
 183         argv++;
 184
 185         if (argc == 3)
 186                 mask = simple_strtoul(argv[1], NULL, 16);
 187
 188         switch (*argv[0]) {
 189         case 'e':       /* Enable */
 190                 do_bridge_reset(1, mask);
 191                 break;
 192         case 'd':       /* Disable */
 193                 do_bridge_reset(0, mask);
 194                 break;
 195         default:
 196                 return CMD_RET_USAGE;
 197         }
 198
 199         return 0;
 200 }
 201
 202 U_BOOT_CMD(bridge, 3, 1, do_bridge,
 203            "SoCFPGA HPS FPGA bridge control",
 204            "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 205            "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 206            ""
 207 );
 208
 209 #endif
 210
 211 static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
 212 {
 213         const void *blob = gd->fdt_blob;
 214         struct fdt_resource r;
 215         int node;
 216         int ret;
 217
 218         node = fdt_node_offset_by_compatible(blob, -1, compat);
 219         if (node < 0)
 220                 return node;
 221
 222         if (!fdtdec_get_is_enabled(blob, node))
 223                 return -ENODEV;
 224
 225         ret = fdt_get_resource(blob, node, "reg", 0, &r);
 226         if (ret)
 227                 return ret;
 228
 229         *base = (phys_addr_t)r.start;
 230
 231         return 0;
 232 }
 233
 234 void socfpga_get_managers_addr(void)
 235 {
 236         int ret;
 237
 238         ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
 239         if (ret)
 240                 hang();
 241 }
 242
 243 phys_addr_t socfpga_get_rstmgr_addr(void)
 244 {
 245         return socfpga_rstmgr_base;
 246 }