arch/arm/mach-socfpga/misc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <hang.h>
   9 #include <asm/io.h>
  10 #include <errno.h>
  11 #include <fdtdec.h>
  12 #include <linux/libfdt.h>
  13 #include <altera.h>
  14 #include <miiphy.h>
  15 #include <netdev.h>
  16 #include <watchdog.h>
  17 #include <asm/arch/misc.h>
  18 #include <asm/arch/reset_manager.h>
  19 #include <asm/arch/scan_manager.h>
  20 #include <asm/arch/system_manager.h>
  21 #include <asm/arch/nic301.h>
  22 #include <asm/arch/scu.h>
  23 #include <asm/pl310.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 phys_addr_t socfpga_clkmgr_base __section(".data");
  28 phys_addr_t socfpga_rstmgr_base __section(".data");
  29 phys_addr_t socfpga_sysmgr_base __section(".data");
  30
  31 #ifdef CONFIG_SYS_L2_PL310
  32 static const struct pl310_regs *const pl310 =
  33         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  34 #endif
  35
  36 struct bsel bsel_str[] = {
  37         { "rsvd", "Reserved", },
  38         { "fpga", "FPGA (HPS2FPGA Bridge)", },
  39         { "nand", "NAND Flash (1.8V)", },
  40         { "nand", "NAND Flash (3.0V)", },
  41         { "sd", "SD/MMC External Transceiver (1.8V)", },
  42         { "sd", "SD/MMC Internal Transceiver (3.0V)", },
  43         { "qspi", "QSPI Flash (1.8V)", },
  44         { "qspi", "QSPI Flash (3.0V)", },
  45 };
  46
  47 int dram_init(void)
  48 {
  49         if (fdtdec_setup_mem_size_base() != 0)
  50                 return -EINVAL;
  51
  52         return 0;
  53 }
  54
  55 void enable_caches(void)
  56 {
  57 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  58         icache_enable();
  59 #endif
  60 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  61         dcache_enable();
  62 #endif
  63 }
  64
  65 #ifdef CONFIG_SYS_L2_PL310
  66 void v7_outer_cache_enable(void)
  67 {
  68         struct udevice *dev;
  69
  70         if (uclass_get_device(UCLASS_CACHE, 0, &dev))
  71                 pr_err("cache controller driver NOT found!\n");
  72 }
  73
  74 void v7_outer_cache_disable(void)
  75 {
  76         /* Disable the L2 cache */
  77         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  78 }
  79
  80 void socfpga_pl310_clear(void)
  81 {
  82         u32 mask = 0xff, ena = 0;
  83
  84         icache_enable();
  85
  86         /* Disable the L2 cache */
  87         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  88
  89         writel(0x0, &pl310->pl310_tag_latency_ctrl);
  90         writel(0x10, &pl310->pl310_data_latency_ctrl);
  91
  92         /* enable BRESP, instruction and data prefetch, full line of zeroes */
  93         setbits_le32(&pl310->pl310_aux_ctrl,
  94                      L310_AUX_CTRL_DATA_PREFETCH_MASK |
  95                      L310_AUX_CTRL_INST_PREFETCH_MASK |
  96                      L310_SHARED_ATT_OVERRIDE_ENABLE);
  97
  98         /* Enable the L2 cache */
  99         ena = readl(&pl310->pl310_ctrl);
 100         ena |= L2X0_CTRL_EN;
 101
 102         /*
 103          * Invalidate the PL310 L2 cache. Keep the invalidation code
 104          * entirely in L1 I-cache to avoid any bus traffic through
 105          * the L2.
 106          */
 107         asm volatile(
 108                 ".align 5                       \n"
 109                 "       b       3f              \n"
 110                 "1:     str     %1,     [%4]    \n"
 111                 "       dsb                     \n"
 112                 "       isb                     \n"
 113                 "       str     %0,     [%2]    \n"
 114                 "       dsb                     \n"
 115                 "       isb                     \n"
 116                 "2:     ldr     %0,     [%2]    \n"
 117                 "       cmp     %0,     #0      \n"
 118                 "       bne     2b              \n"
 119                 "       str     %0,     [%3]    \n"
 120                 "       dsb                     \n"
 121                 "       isb                     \n"
 122                 "       b       4f              \n"
 123                 "3:     b       1b              \n"
 124                 "4:     nop                     \n"
 125         : "+r"(mask), "+r"(ena)
 126         : "r"(&pl310->pl310_inv_way),
 127           "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
 128         : "memory", "cc");
 129
 130         /* Disable the L2 cache */
 131         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 132 }
 133 #endif
 134
 135 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 136 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 137 int overwrite_console(void)
 138 {
 139         return 0;
 140 }
 141 #endif
 142
 143 #ifdef CONFIG_FPGA
 144 /* add device descriptor to FPGA device table */
 145 void socfpga_fpga_add(void *fpga_desc)
 146 {
 147         fpga_init();
 148         fpga_add(fpga_altera, fpga_desc);
 149 }
 150 #endif
 151
 152 int arch_cpu_init(void)
 153 {
 154         socfpga_get_managers_addr();
 155
 156 #ifdef CONFIG_HW_WATCHDOG
 157         /*
 158          * In case the watchdog is enabled, make sure to (re-)configure it
 159          * so that the defined timeout is valid. Otherwise the SPL (Perloader)
 160          * timeout value is still active which might too short for Linux
 161          * booting.
 162          */
 163         hw_watchdog_init();
 164 #else
 165         /*
 166          * If the HW watchdog is NOT enabled, make sure it is not running,
 167          * for example because it was enabled in the preloader. This might
 168          * trigger a watchdog-triggered reboot of Linux kernel later.
 169          * Toggle watchdog reset, so watchdog in not running state.
 170          */
 171         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 172         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 173 #endif
 174
 175         return 0;
 176 }
 177
 178 #ifndef CONFIG_SPL_BUILD
 179 static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 180 {
 181         unsigned int mask = ~0;
 182
 183         if (argc < 2 || argc > 3)
 184                 return CMD_RET_USAGE;
 185
 186         argv++;
 187
 188         if (argc == 3)
 189                 mask = simple_strtoul(argv[1], NULL, 16);
 190
 191         switch (*argv[0]) {
 192         case 'e':       /* Enable */
 193                 do_bridge_reset(1, mask);
 194                 break;
 195         case 'd':       /* Disable */
 196                 do_bridge_reset(0, mask);
 197                 break;
 198         default:
 199                 return CMD_RET_USAGE;
 200         }
 201
 202         return 0;
 203 }
 204
 205 U_BOOT_CMD(bridge, 3, 1, do_bridge,
 206            "SoCFPGA HPS FPGA bridge control",
 207            "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 208            "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 209            ""
 210 );
 211
 212 #endif
 213
 214 static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
 215 {
 216         const void *blob = gd->fdt_blob;
 217         struct fdt_resource r;
 218         int node;
 219         int ret;
 220
 221         node = fdt_node_offset_by_compatible(blob, -1, compat);
 222         if (node < 0)
 223                 return node;
 224
 225         if (!fdtdec_get_is_enabled(blob, node))
 226                 return -ENODEV;
 227
 228         ret = fdt_get_resource(blob, node, "reg", 0, &r);
 229         if (ret)
 230                 return ret;
 231
 232         *base = (phys_addr_t)r.start;
 233
 234         return 0;
 235 }
 236
 237 void socfpga_get_managers_addr(void)
 238 {
 239         int ret;
 240
 241         ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
 242         if (ret)
 243                 hang();
 244
 245         ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
 246         if (ret)
 247                 hang();
 248
 249 #ifdef CONFIG_TARGET_SOCFPGA_AGILEX
 250         ret = socfpga_get_base_addr("intel,agilex-clkmgr",
 251                                     &socfpga_clkmgr_base);
 252 #else
 253         ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
 254 #endif
 255         if (ret)
 256                 hang();
 257 }
 258
 259 phys_addr_t socfpga_get_rstmgr_addr(void)
 260 {
 261         return socfpga_rstmgr_base;
 262 }
 263
 264 phys_addr_t socfpga_get_sysmgr_addr(void)
 265 {
 266         return socfpga_sysmgr_base;
 267 }
 268
 269 phys_addr_t socfpga_get_clkmgr_addr(void)
 270 {
 271         return socfpga_clkmgr_base;
 272 }