1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
10 #include <asm/arch/mailbox_s10.h>
11 #include <asm/arch/system_manager.h>
12 #include <asm/secure.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 #define MBOX_READL(reg) \
17 readl(SOCFPGA_MAILBOX_ADDRESS + (reg))
19 #define MBOX_WRITEL(data, reg) \
20 writel(data, SOCFPGA_MAILBOX_ADDRESS + (reg))
22 #define MBOX_READ_RESP_BUF(rout) \
23 MBOX_READL(MBOX_RESP_BUF + ((rout) * sizeof(u32)))
25 #define MBOX_WRITE_CMD_BUF(data, cin) \
26 MBOX_WRITEL(data, MBOX_CMD_BUF + ((cin) * sizeof(u32)))
28 static __always_inline int mbox_polling_resp(u32 rout)
34 rin = MBOX_READL(MBOX_RIN);
44 /* Check for available slot and write to circular buffer.
45 * It also update command valid offset (cin) register.
47 static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len,
54 cin = MBOX_READL(MBOX_CIN) % MBOX_CMD_BUFFER_SIZE;
55 cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE;
57 /* if command buffer is full or not enough free space
58 * to fit the data. Note, len is in u32 unit.
60 if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
61 ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
62 MBOX_CMD_BUFFER_SIZE) < (len + 1))
65 /* write header to circular buffer */
66 MBOX_WRITE_CMD_BUF(header, cin++);
67 /* wrapping around when it reach the buffer size */
68 cin %= MBOX_CMD_BUFFER_SIZE;
71 for (i = 0; i < len; i++) {
72 MBOX_WRITE_CMD_BUF(arg[i], cin++);
73 /* wrapping around when it reach the buffer size */
74 cin %= MBOX_CMD_BUFFER_SIZE;
77 /* write command valid offset */
78 MBOX_WRITEL(cin, MBOX_CIN);
83 /* Check the command and fill it into circular buffer */
84 static __always_inline int mbox_prepare_cmd_only(u8 id, u32 cmd,
85 u8 is_indirect, u32 len,
91 /* Total length is command + argument length */
92 if ((len + 1) > MBOX_CMD_BUFFER_SIZE)
95 if (cmd > MBOX_MAX_CMD_INDEX)
98 header = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id, len,
99 (is_indirect) ? 1 : 0, cmd);
101 ret = mbox_fill_cmd_circular_buff(header, len, arg);
106 /* Send command only without waiting for responses from SDM */
107 static __always_inline int mbox_send_cmd_only_common(u8 id, u32 cmd,
108 u8 is_indirect, u32 len,
111 int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
113 MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
118 /* Return number of responses received in buffer */
119 static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
125 /* clear doorbell from SDM if it was SET */
126 if (MBOX_READL(MBOX_DOORBELL_FROM_SDM) & 1)
127 MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
129 /* read current response offset */
130 rout = MBOX_READL(MBOX_ROUT);
131 /* read response valid offset */
132 rin = MBOX_READL(MBOX_RIN);
134 while (rin != rout && (resp_len < resp_buf_max_len)) {
135 /* Response received */
137 resp_buf[resp_len++] = MBOX_READ_RESP_BUF(rout);
140 /* wrapping around when it reach the buffer size */
141 rout %= MBOX_RESP_BUFFER_SIZE;
142 /* update next ROUT */
143 MBOX_WRITEL(rout, MBOX_ROUT);
149 /* Support one command and up to 31 words argument length only */
150 static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect,
151 u32 len, u32 *arg, u8 urgent,
164 /* Read status because it is toggled */
165 status = MBOX_READL(MBOX_STATUS) & MBOX_STATUS_UA_MSK;
166 /* Write urgent command to urgent register */
167 MBOX_WRITEL(cmd, MBOX_URG);
169 ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
175 MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
180 /* Wait for doorbell from SDM */
181 while (!MBOX_READL(MBOX_DOORBELL_FROM_SDM) && ret--)
186 /* clear interrupt */
187 MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
190 u32 new_status = MBOX_READL(MBOX_STATUS);
192 /* Urgent ACK is toggled */
193 if ((new_status & MBOX_STATUS_UA_MSK) ^ status)
199 /* read current response offset */
200 rout = MBOX_READL(MBOX_ROUT);
202 /* read response valid offset */
203 rin = MBOX_READL(MBOX_RIN);
206 /* Response received */
207 resp = MBOX_READ_RESP_BUF(rout);
209 /* wrapping around when it reach the buffer size */
210 rout %= MBOX_RESP_BUFFER_SIZE;
211 /* update next ROUT */
212 MBOX_WRITEL(rout, MBOX_ROUT);
214 /* check client ID and ID */
215 if ((MBOX_RESP_CLIENT_GET(resp) ==
216 MBOX_CLIENT_ID_UBOOT) &&
217 (MBOX_RESP_ID_GET(resp) == id)) {
218 ret = MBOX_RESP_ERR_GET(resp);
223 buf_len = *resp_buf_len;
229 resp_len = MBOX_RESP_LEN_GET(resp);
231 ret = mbox_polling_resp(rout);
234 /* we need to process response buffer
235 * even caller doesn't need it
237 resp = MBOX_READ_RESP_BUF(rout);
240 rout %= MBOX_RESP_BUFFER_SIZE;
241 MBOX_WRITEL(rout, MBOX_ROUT);
243 /* copy response to buffer */
244 resp_buf[*resp_buf_len] = resp;
261 /* enable mailbox interrupts */
262 MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS);
264 /* Ensure urgent request is cleared */
265 MBOX_WRITEL(0, MBOX_URG);
267 /* Ensure the Doorbell Interrupt is cleared */
268 MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
270 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, MBOX_CMD_DIRECT, 0,
275 /* Renable mailbox interrupts after MBOX_RESTART */
276 MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS);
281 #ifdef CONFIG_CADENCE_QSPI
282 int mbox_qspi_close(void)
284 return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_CLOSE, MBOX_CMD_DIRECT,
285 0, NULL, 0, 0, NULL);
288 int mbox_qspi_open(void)
294 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT,
295 0, NULL, 0, 0, NULL);
297 /* retry again by closing and reopen the QSPI again */
298 ret = mbox_qspi_close();
302 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN,
303 MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL);
308 /* HPS will directly control the QSPI controller, no longer mailbox */
310 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_DIRECT, MBOX_CMD_DIRECT,
311 0, NULL, 0, (u32 *)&resp_buf_len,
316 /* We are getting QSPI ref clock and set into sysmgr boot register */
317 printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
319 socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
328 #endif /* CONFIG_CADENCE_QSPI */
330 int mbox_reset_cold(void)
334 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
335 0, NULL, 0, 0, NULL);
337 /* mailbox sent failure, wait for watchdog to kick in */
343 /* Accepted commands: CONFIG_STATUS or RECONFIG_STATUS */
344 static __always_inline int mbox_get_fpga_config_status_common(u32 cmd)
346 u32 reconfig_status_resp_len;
347 u32 reconfig_status_resp[RECONFIG_STATUS_RESPONSE_LEN];
350 reconfig_status_resp_len = RECONFIG_STATUS_RESPONSE_LEN;
351 ret = mbox_send_cmd_common(MBOX_ID_UBOOT, cmd,
352 MBOX_CMD_DIRECT, 0, NULL, 0,
353 &reconfig_status_resp_len,
354 reconfig_status_resp);
359 /* Check for any error */
360 ret = reconfig_status_resp[RECONFIG_STATUS_STATE];
361 if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
364 /* Make sure nStatus is not 0 */
365 ret = reconfig_status_resp[RECONFIG_STATUS_PIN_STATUS];
366 if (!(ret & RCF_PIN_STATUS_NSTATUS))
367 return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
369 ret = reconfig_status_resp[RECONFIG_STATUS_SOFTFUNC_STATUS];
370 if (ret & RCF_SOFTFUNC_STATUS_SEU_ERROR)
371 return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
373 if ((ret & RCF_SOFTFUNC_STATUS_CONF_DONE) &&
374 (ret & RCF_SOFTFUNC_STATUS_INIT_DONE) &&
375 !reconfig_status_resp[RECONFIG_STATUS_STATE])
376 return 0; /* configuration success */
378 return MBOX_CFGSTAT_STATE_CONFIG;
381 int mbox_get_fpga_config_status(u32 cmd)
383 return mbox_get_fpga_config_status_common(cmd);
386 int __secure mbox_get_fpga_config_status_psci(u32 cmd)
388 return mbox_get_fpga_config_status_common(cmd);
391 int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
392 u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
394 return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent,
395 resp_buf_len, resp_buf);
398 int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
399 u32 *arg, u8 urgent, u32 *resp_buf_len,
402 return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent,
403 resp_buf_len, resp_buf);
406 int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg)
408 return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
411 int __secure mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
414 return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
417 int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
419 return __mbox_rcv_resp(resp_buf, resp_buf_max_len);
422 int __secure mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len)
424 return __mbox_rcv_resp(resp_buf, resp_buf_max_len);