arch/arm/mach-socfpga/include/mach/system_manager.h

   1 /*
   2  * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _SYSTEM_MANAGER_H_
   8 #define _SYSTEM_MANAGER_H_
   9
  10 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0)
  11 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO     (1 << 1)
  12 #define SYSMGR_ECC_OCRAM_EN     (1 << 0)
  13 #define SYSMGR_ECC_OCRAM_SERR   (1 << 3)
  14 #define SYSMGR_ECC_OCRAM_DERR   (1 << 4)
  15 #define SYSMGR_FPGAINTF_USEFPGA 0x1
  16 #define SYSMGR_FPGAINTF_SPIM0   (1 << 0)
  17 #define SYSMGR_FPGAINTF_SPIM1   (1 << 1)
  18 #define SYSMGR_FPGAINTF_EMAC0   (1 << 2)
  19 #define SYSMGR_FPGAINTF_EMAC1   (1 << 3)
  20 #define SYSMGR_FPGAINTF_NAND    (1 << 4)
  21 #define SYSMGR_FPGAINTF_SDMMC   (1 << 5)
  22
  23 #define SYSMGR_SDMMC_DRVSEL_SHIFT       0
  24
  25 /* EMAC Group Bit definitions */
  26 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII        0x0
  27 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII           0x1
  28 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII            0x2
  29
  30 #define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB                 0
  31 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB                 2
  32 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK                 0x3
  33
  34 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  35 #include <asm/arch/system_manager_gen5.h>
  36 #endif
  37
  38 #define SYSMGR_GET_BOOTINFO_BSEL(bsel)          \
  39                 (((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
  40
  41 #endif /* _SYSTEM_MANAGER_H_ */