arch/arm/mach-socfpga/include/mach/system_manager.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #ifndef _SYSTEM_MANAGER_H_
   7 #define _SYSTEM_MANAGER_H_
   8
   9 phys_addr_t socfpga_get_sysmgr_addr(void);
  10
  11 #if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
  12 #include <asm/arch/system_manager_soc64.h>
  13 #else
  14 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
  15 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO     BIT(1)
  16 #define SYSMGR_ECC_OCRAM_EN     BIT(0)
  17 #define SYSMGR_ECC_OCRAM_SERR   BIT(3)
  18 #define SYSMGR_ECC_OCRAM_DERR   BIT(4)
  19 #define SYSMGR_FPGAINTF_USEFPGA 0x1
  20 #define SYSMGR_FPGAINTF_SPIM0   BIT(0)
  21 #define SYSMGR_FPGAINTF_SPIM1   BIT(1)
  22 #define SYSMGR_FPGAINTF_EMAC0   BIT(2)
  23 #define SYSMGR_FPGAINTF_EMAC1   BIT(3)
  24 #define SYSMGR_FPGAINTF_NAND    BIT(4)
  25 #define SYSMGR_FPGAINTF_SDMMC   BIT(5)
  26
  27 #define SYSMGR_SDMMC_DRVSEL_SHIFT       0
  28
  29 /* EMAC Group Bit definitions */
  30 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII        0x0
  31 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII           0x1
  32 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII            0x2
  33
  34 #define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB                 0
  35 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB                 2
  36 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK                 0x3
  37
  38 /* For dedicated IO configuration */
  39 /* Voltage select enums */
  40 #define VOLTAGE_SEL_3V          0x0
  41 #define VOLTAGE_SEL_1P8V        0x1
  42 #define VOLTAGE_SEL_2P5V        0x2
  43
  44 /* Input buffer enable */
  45 #define INPUT_BUF_DISABLE       0
  46 #define INPUT_BUF_1P8V          1
  47 #define INPUT_BUF_2P5V3V        2
  48
  49 /* Weak pull up enable */
  50 #define WK_PU_DISABLE           0
  51 #define WK_PU_ENABLE            1
  52
  53 /* Pull up slew rate control */
  54 #define PU_SLW_RT_SLOW          0
  55 #define PU_SLW_RT_FAST          1
  56 #define PU_SLW_RT_DEFAULT       PU_SLW_RT_SLOW
  57
  58 /* Pull down slew rate control */
  59 #define PD_SLW_RT_SLOW          0
  60 #define PD_SLW_RT_FAST          1
  61 #define PD_SLW_RT_DEFAULT       PD_SLW_RT_SLOW
  62
  63 /* Drive strength control */
  64 #define PU_DRV_STRG_DEFAULT     0x10
  65 #define PD_DRV_STRG_DEFAULT     0x10
  66
  67 /* bit position */
  68 #define PD_DRV_STRG_LSB         0
  69 #define PD_SLW_RT_LSB           5
  70 #define PU_DRV_STRG_LSB         8
  71 #define PU_SLW_RT_LSB           13
  72 #define WK_PU_LSB               16
  73 #define INPUT_BUF_LSB           17
  74 #define BIAS_TRIM_LSB           19
  75 #define VOLTAGE_SEL_LSB         0
  76
  77 #define ALT_SYSMGR_NOC_H2F_SET_MSK      BIT(0)
  78 #define ALT_SYSMGR_NOC_LWH2F_SET_MSK    BIT(4)
  79 #define ALT_SYSMGR_NOC_F2H_SET_MSK      BIT(8)
  80 #define ALT_SYSMGR_NOC_F2SDR0_SET_MSK   BIT(16)
  81 #define ALT_SYSMGR_NOC_F2SDR1_SET_MSK   BIT(20)
  82 #define ALT_SYSMGR_NOC_F2SDR2_SET_MSK   BIT(24)
  83 #define ALT_SYSMGR_NOC_TMO_EN_SET_MSK   BIT(0)
  84
  85 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK       BIT(1)
  86 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK       BIT(1)
  87
  88 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  89 #include <asm/arch/system_manager_gen5.h>
  90 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  91 #include <asm/arch/system_manager_arria10.h>
  92 #endif
  93
  94 #define SYSMGR_GET_BOOTINFO_BSEL(bsel)          \
  95                 (((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
  96 #endif
  97 #endif /* _SYSTEM_MANAGER_H_ */