arch/arm/mach-socfpga/include/mach/sdram_s10.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef _SDRAM_S10_H_
   8 #define _SDRAM_S10_H_
   9
  10 phys_size_t sdram_calculate_size(void);
  11 int sdram_mmr_init_full(unsigned int sdr_phy_reg);
  12 int sdram_calibration_full(void);
  13
  14 #define DDR_TWR                         15
  15 #define DDR_READ_LATENCY_DELAY          40
  16 #define DDR_ACTIVATE_FAWBANK            0x1
  17
  18 /* ECC HMC registers */
  19 #define DDRIOCTRL                       0x8
  20 #define DDRCALSTAT                      0xc
  21 #define DRAMADDRWIDTH                   0xe0
  22 #define ECCCTRL1                        0x100
  23 #define ECCCTRL2                        0x104
  24 #define ERRINTEN                        0x110
  25 #define ERRINTENS                       0x114
  26 #define INTMODE                         0x11c
  27 #define INTSTAT                         0x120
  28 #define AUTOWB_CORRADDR                 0x138
  29 #define ECC_REG2WRECCDATABUS            0x144
  30 #define ECC_DIAGON                      0x150
  31 #define ECC_DECSTAT                     0x154
  32 #define HPSINTFCSEL                     0x210
  33 #define RSTHANDSHAKECTRL                0x214
  34 #define RSTHANDSHAKESTAT                0x218
  35
  36 #define DDR_HMC_DDRIOCTRL_IOSIZE_MSK            0x00000003
  37 #define DDR_HMC_DDRCALSTAT_CAL_MSK              BIT(0)
  38 #define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK      BIT(16)
  39 #define DDR_HMC_ECCCTL_CNT_RST_SET_MSK          BIT(8)
  40 #define DDR_HMC_ECCCTL_ECC_EN_SET_MSK           BIT(0)
  41 #define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK          BIT(8)
  42 #define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK          BIT(0)
  43 #define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16)
  44 #define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK  BIT(0)
  45 #define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK   BIT(0)
  46 #define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK   BIT(1)
  47 #define DDR_HMC_INTSTAT_SERRPENA_SET_MSK        BIT(0)
  48 #define DDR_HMC_INTSTAT_DERRPENA_SET_MSK        BIT(1)
  49 #define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK      BIT(16)
  50 #define DDR_HMC_INTMODE_INTMODE_SET_MSK         BIT(0)
  51 #define DDR_HMC_RSTHANDSHAKE_MASK               0x000000ff
  52 #define DDR_HMC_CORE2SEQ_INT_REQ                0xF
  53 #define DDR_HMC_SEQ2CORE_INT_RESP_MASK          BIT(3)
  54 #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK         0x001f1f1f
  55
  56 #define DDR_HMC_ERRINTEN_INTMASK                                \
  57                 (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK |        \
  58                  DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
  59
  60 /* NOC DDR scheduler */
  61 #define DDR_SCH_ID_COREID               0
  62 #define DDR_SCH_ID_REVID                0x4
  63 #define DDR_SCH_DDRCONF                 0x8
  64 #define DDR_SCH_DDRTIMING               0xc
  65 #define DDR_SCH_DDRMODE                 0x10
  66 #define DDR_SCH_READ_LATENCY            0x14
  67 #define DDR_SCH_ACTIVATE                0x38
  68 #define DDR_SCH_DEVTODEV                0x3c
  69 #define DDR_SCH_DDR4TIMING              0x40
  70
  71 #define DDR_SCH_DDRTIMING_ACTTOACT_OFF          0
  72 #define DDR_SCH_DDRTIMING_RDTOMISS_OFF          6
  73 #define DDR_SCH_DDRTIMING_WRTOMISS_OFF          12
  74 #define DDR_SCH_DDRTIMING_BURSTLEN_OFF          18
  75 #define DDR_SCH_DDRTIMING_RDTOWR_OFF            21
  76 #define DDR_SCH_DDRTIMING_WRTORD_OFF            26
  77 #define DDR_SCH_DDRTIMING_BWRATIO_OFF           31
  78 #define DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF      1
  79 #define DDR_SCH_ACTIVATE_RRD_OFF                0
  80 #define DDR_SCH_ACTIVATE_FAW_OFF                4
  81 #define DDR_SCH_ACTIVATE_FAWBANK_OFF            10
  82 #define DDR_SCH_DEVTODEV_BUSRDTORD_OFF          0
  83 #define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF          2
  84 #define DDR_SCH_DEVTODEV_BUSWRTORD_OFF          4
  85
  86 /* HMC MMR IO48 registers */
  87 #define CTRLCFG0                        0x28
  88 #define CTRLCFG1                        0x2c
  89 #define DRAMTIMING0                     0x50
  90 #define CALTIMING0                      0x7c
  91 #define CALTIMING1                      0x80
  92 #define CALTIMING2                      0x84
  93 #define CALTIMING3                      0x88
  94 #define CALTIMING4                      0x8c
  95 #define CALTIMING9                      0xa0
  96 #define DRAMADDRW                       0xa8
  97 #define DRAMSTS                         0xec
  98 #define NIOSRESERVED0                   0x110
  99 #define NIOSRESERVED1                   0x114
 100 #define NIOSRESERVED2                   0x118
 101
 102 #define DRAMADDRW_CFG_COL_ADDR_WIDTH(x)                 \
 103         (((x) >> 0) & 0x1F)
 104 #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x)                 \
 105         (((x) >> 5) & 0x1F)
 106 #define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x)                \
 107         (((x) >> 10) & 0xF)
 108 #define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x)            \
 109         (((x) >> 14) & 0x3)
 110 #define DRAMADDRW_CFG_CS_ADDR_WIDTH(x)                  \
 111         (((x) >> 16) & 0x7)
 112
 113 #define CTRLCFG0_CFG_MEMTYPE(x)                         \
 114         (((x) >> 0) & 0xF)
 115 #define CTRLCFG0_CFG_DIMM_TYPE(x)                       \
 116         (((x) >> 4) & 0x7)
 117 #define CTRLCFG0_CFG_AC_POS(x)                          \
 118         (((x) >> 7) & 0x3)
 119 #define CTRLCFG0_CFG_CTRL_BURST_LEN(x)                  \
 120         (((x) >> 9) & 0x1F)
 121
 122 #define CTRLCFG1_CFG_DBC3_BURST_LEN(x)                  \
 123         (((x) >> 0) & 0x1F)
 124 #define CTRLCFG1_CFG_ADDR_ORDER(x)                      \
 125         (((x) >> 5) & 0x3)
 126 #define CTRLCFG1_CFG_CTRL_EN_ECC(x)                     \
 127         (((x) >> 7) & 0x1)
 128
 129 #define DRAMTIMING0_CFG_TCL(x)                          \
 130         (((x) >> 0) & 0x7F)
 131
 132 #define CALTIMING0_CFG_ACT_TO_RDWR(x)                   \
 133         (((x) >> 0) & 0x3F)
 134 #define CALTIMING0_CFG_ACT_TO_PCH(x)                    \
 135         (((x) >> 6) & 0x3F)
 136 #define CALTIMING0_CFG_ACT_TO_ACT(x)                    \
 137         (((x) >> 12) & 0x3F)
 138 #define CALTIMING0_CFG_ACT_TO_ACT_DB(x)                 \
 139         (((x) >> 18) & 0x3F)
 140
 141 #define CALTIMING1_CFG_RD_TO_RD(x)                      \
 142         (((x) >> 0) & 0x3F)
 143 #define CALTIMING1_CFG_RD_TO_RD_DC(x)                   \
 144         (((x) >> 6) & 0x3F)
 145 #define CALTIMING1_CFG_RD_TO_RD_DB(x)                   \
 146         (((x) >> 12) & 0x3F)
 147 #define CALTIMING1_CFG_RD_TO_WR(x)                      \
 148         (((x) >> 18) & 0x3F)
 149 #define CALTIMING1_CFG_RD_TO_WR_DC(x)                   \
 150         (((x) >> 24) & 0x3F)
 151
 152 #define CALTIMING2_CFG_RD_TO_WR_DB(x)                   \
 153         (((x) >> 0) & 0x3F)
 154 #define CALTIMING2_CFG_RD_TO_WR_PCH(x)                  \
 155         (((x) >> 6) & 0x3F)
 156 #define CALTIMING2_CFG_RD_AP_TO_VALID(x)                \
 157         (((x) >> 12) & 0x3F)
 158 #define CALTIMING2_CFG_WR_TO_WR(x)                      \
 159         (((x) >> 18) & 0x3F)
 160 #define CALTIMING2_CFG_WR_TO_WR_DC(x)                   \
 161         (((x) >> 24) & 0x3F)
 162
 163 #define CALTIMING3_CFG_WR_TO_WR_DB(x)                   \
 164         (((x) >> 0) & 0x3F)
 165 #define CALTIMING3_CFG_WR_TO_RD(x)                      \
 166         (((x) >> 6) & 0x3F)
 167 #define CALTIMING3_CFG_WR_TO_RD_DC(x)                   \
 168         (((x) >> 12) & 0x3F)
 169 #define CALTIMING3_CFG_WR_TO_RD_DB(x)                   \
 170         (((x) >> 18) & 0x3F)
 171 #define CALTIMING3_CFG_WR_TO_PCH(x)                     \
 172         (((x) >> 24) & 0x3F)
 173
 174 #define CALTIMING4_CFG_WR_AP_TO_VALID(x)                \
 175         (((x) >> 0) & 0x3F)
 176 #define CALTIMING4_CFG_PCH_TO_VALID(x)                  \
 177         (((x) >> 6) & 0x3F)
 178 #define CALTIMING4_CFG_PCH_ALL_TO_VALID(x)              \
 179         (((x) >> 12) & 0x3F)
 180 #define CALTIMING4_CFG_ARF_TO_VALID(x)                  \
 181         (((x) >> 18) & 0xFF)
 182 #define CALTIMING4_CFG_PDN_TO_VALID(x)                  \
 183         (((x) >> 26) & 0x3F)
 184
 185 #define CALTIMING9_CFG_4_ACT_TO_ACT(x)                  \
 186         (((x) >> 0) & 0xFF)
 187
 188 /* Firewall DDR scheduler MPFE */
 189 #define FW_HMC_ADAPTOR_REG_ADDR                 0xf8020004
 190 #define FW_HMC_ADAPTOR_MPU_MASK                 BIT(0)
 191
 192 #endif /* _SDRAM_S10_H_ */