1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright Altera Corporation (C) 2014-2015
5 #ifndef _SOCFPGA_SDRAM_GEN5_H_
6 #define _SOCFPGA_SDRAM_GEN5_H_
10 const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
12 void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
13 void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
14 const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
15 const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
16 const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
18 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
20 struct socfpga_sdr_ctrl {
25 u32 dram_timing4; /* 0x10 */
30 u32 dram_addrw; /* 0x2c */
31 u32 dram_if_width; /* 0x30 */
35 u32 sbe_count; /* 0x40 */
39 u32 drop_addr; /* 0x50 */
43 u32 ctrl_width; /* 0x60 */
47 u32 rfifo_cmap; /* 0x70 */
51 u32 fpgaport_rst; /* 0x80 */
55 u32 prot_rule_addr; /* 0x90 */
60 u32 mp_priority; /* 0xac */
61 u32 mp_weight0; /* 0xb0 */
65 u32 mp_pacing0; /* 0xc0 */
69 u32 mp_threshold0; /* 0xd0 */
73 u32 phy_ctrl0; /* 0x150 */
78 /* SDRAM configuration structure for the SPL. */
79 struct socfpga_sdram_config {
119 struct socfpga_sdram_rw_mgr_config {
121 u8 activate_0_and_1_wait1;
122 u8 activate_0_and_1_wait2;
126 u8 guaranteed_read_cont;
128 u8 guaranteed_write_wait0;
129 u8 guaranteed_write_wait1;
130 u8 guaranteed_write_wait2;
131 u8 guaranteed_write_wait3;
135 u8 init_reset_0_cke_0;
136 u8 init_reset_1_cke_0;
137 u8 lfsr_wr_rd_bank_0;
138 u8 lfsr_wr_rd_bank_0_data;
139 u8 lfsr_wr_rd_bank_0_dqs;
140 u8 lfsr_wr_rd_bank_0_nop;
141 u8 lfsr_wr_rd_bank_0_wait;
142 u8 lfsr_wr_rd_bank_0_wl_1;
143 u8 lfsr_wr_rd_dm_bank_0;
144 u8 lfsr_wr_rd_dm_bank_0_data;
145 u8 lfsr_wr_rd_dm_bank_0_dqs;
146 u8 lfsr_wr_rd_dm_bank_0_nop;
147 u8 lfsr_wr_rd_dm_bank_0_wait;
148 u8 lfsr_wr_rd_dm_bank_0_wl_1;
150 u8 mrs0_dll_reset_mirr;
168 u8 true_mem_data_mask_width;
169 u8 mem_address_mirroring;
170 u8 mem_data_mask_width;
172 u8 mem_dq_per_read_dqs;
173 u8 mem_dq_per_write_dqs;
174 u8 mem_if_read_dqs_width;
175 u8 mem_if_write_dqs_width;
176 u8 mem_number_of_cs_per_dimm;
177 u8 mem_number_of_ranks;
178 u8 mem_virtual_groups_per_read_dqs;
179 u8 mem_virtual_groups_per_write_dqs;
182 struct socfpga_sdram_io_config {
183 u16 delay_per_opa_tap;
184 u8 delay_per_dchain_tap;
185 u8 delay_per_dqs_en_dchain_tap;
187 u8 dqdqs_out_phase_max;
189 u8 dqs_en_delay_offset;
195 u8 io_out1_delay_max;
196 u8 io_out2_delay_max;
197 u8 shift_dqs_en_when_shift_dqs;
200 struct socfpga_sdram_misc_config {
201 u32 reg_file_init_seq_signature;
203 u8 calib_lfifo_offset;
204 u8 calib_vfifo_offset;
205 u8 enable_super_quick_calibration;
206 u8 max_latency_count_width;
207 u8 read_valid_fifo_size;
216 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
217 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
218 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
219 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
220 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
221 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
222 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
223 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
224 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
225 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
226 #define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
227 #define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
228 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
229 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
230 #define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
231 #define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
232 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
233 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
234 /* Register template: sdr::ctrlgrp::dramtiming1 */
235 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
236 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
237 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
238 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
239 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
240 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
241 #define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
242 #define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
243 #define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
244 #define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
245 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
246 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
247 /* Register template: sdr::ctrlgrp::dramtiming2 */
248 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
249 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
250 #define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
251 #define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
252 #define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
253 #define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
254 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
255 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
256 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
257 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
258 /* Register template: sdr::ctrlgrp::dramtiming3 */
259 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
260 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
261 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
262 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
263 #define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
264 #define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
265 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
266 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
267 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
268 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
269 /* Register template: sdr::ctrlgrp::dramtiming4 */
270 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
271 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
272 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
273 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
274 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
275 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
276 /* Register template: sdr::ctrlgrp::lowpwrtiming */
277 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
278 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
279 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
280 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
281 /* Register template: sdr::ctrlgrp::dramaddrw */
282 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
283 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
284 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
285 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
286 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
287 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
288 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
289 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
290 /* Register template: sdr::ctrlgrp::dramifwidth */
291 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
292 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
293 /* Register template: sdr::ctrlgrp::dramdevwidth */
294 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
295 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
296 /* Register template: sdr::ctrlgrp::dramintr */
297 #define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
298 #define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
299 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
300 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
301 /* Register template: sdr::ctrlgrp::staticcfg */
302 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
303 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
304 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
305 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
306 #define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
307 #define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
308 /* Register template: sdr::ctrlgrp::ctrlwidth */
309 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
310 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
311 /* Register template: sdr::ctrlgrp::cportwidth */
312 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
313 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
314 /* Register template: sdr::ctrlgrp::cportwmap */
315 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
316 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
317 /* Register template: sdr::ctrlgrp::cportrmap */
318 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
319 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
320 /* Register template: sdr::ctrlgrp::rfifocmap */
321 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
322 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
323 /* Register template: sdr::ctrlgrp::wfifocmap */
324 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
325 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
326 /* Register template: sdr::ctrlgrp::cportrdwr */
327 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
328 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
329 /* Register template: sdr::ctrlgrp::portcfg */
330 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
331 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
332 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
333 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
334 /* Register template: sdr::ctrlgrp::fifocfg */
335 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
336 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
337 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
338 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
339 /* Register template: sdr::ctrlgrp::mppriority */
340 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
341 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
342 /* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
343 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
344 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
345 /* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
346 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
347 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
348 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
349 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
350 /* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
351 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
352 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
353 /* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
354 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
355 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
356 /* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
357 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
358 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
359 /* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
360 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
361 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
362 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
363 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
364 /* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
365 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
366 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
367 /* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
368 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
369 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
370 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
372 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
374 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
376 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
378 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
380 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
382 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
384 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
386 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
388 /* Register template: sdr::ctrlgrp::remappriority */
389 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
390 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
391 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
392 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
393 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
394 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
395 (((x) << 12) & 0xfffff000)
396 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
397 (((x) << 10) & 0x00000c00)
398 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
399 (((x) << 6) & 0x000000c0)
400 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
401 (((x) << 8) & 0x00000100)
402 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
403 (((x) << 9) & 0x00000200)
404 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
405 (((x) << 4) & 0x00000030)
406 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
407 (((x) << 2) & 0x0000000c)
408 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
409 (((x) << 0) & 0x00000003)
410 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
411 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
412 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
413 (((x) << 12) & 0xfffff000)
414 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
415 (((x) << 0) & 0x00000fff)
416 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
417 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
418 (((x) << 0) & 0x00000fff)
419 /* Register template: sdr::ctrlgrp::dramodt */
420 #define SDR_CTRLGRP_DRAMODT_READ_LSB 4
421 #define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
422 #define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
423 #define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
424 /* Field instance: sdr::ctrlgrp::dramsts */
425 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
426 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
427 /* Register template: sdr::ctrlgrp::extratime1 */
428 #define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
429 #define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
430 #define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
432 /* SDRAM width macro for configuration with ECC */
433 #define SDRAM_WIDTH_32BIT_WITH_ECC 40
434 #define SDRAM_WIDTH_16BIT_WITH_ECC 24
437 #endif /* _SOCFPGA_SDRAM_GEN5_H_ */