arch/arm/mach-socfpga/include/mach/sdram_gen5.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright Altera Corporation (C) 2014-2015
   4  */
   5 #ifndef _SOCFPGA_SDRAM_GEN5_H_
   6 #define _SOCFPGA_SDRAM_GEN5_H_
   7
   8 #ifndef __ASSEMBLY__
   9
  10 const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
  11
  12 void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
  13 void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
  14 const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
  15 const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
  16 const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
  17
  18 #define SDR_CTRLGRP_ADDRESS     (SOCFPGA_SDR_ADDRESS | 0x5000)
  19
  20 struct socfpga_sdr_ctrl {
  21         u32     ctrl_cfg;
  22         u32     dram_timing1;
  23         u32     dram_timing2;
  24         u32     dram_timing3;
  25         u32     dram_timing4;   /* 0x10 */
  26         u32     lowpwr_timing;
  27         u32     dram_odt;
  28         u32     extratime1;
  29         u32     __padding0[3];
  30         u32     dram_addrw;     /* 0x2c */
  31         u32     dram_if_width;  /* 0x30 */
  32         u32     dram_dev_width;
  33         u32     dram_sts;
  34         u32     dram_intr;
  35         u32     sbe_count;      /* 0x40 */
  36         u32     dbe_count;
  37         u32     err_addr;
  38         u32     drop_count;
  39         u32     drop_addr;      /* 0x50 */
  40         u32     lowpwr_eq;
  41         u32     lowpwr_ack;
  42         u32     static_cfg;
  43         u32     ctrl_width;     /* 0x60 */
  44         u32     cport_width;
  45         u32     cport_wmap;
  46         u32     cport_rmap;
  47         u32     rfifo_cmap;     /* 0x70 */
  48         u32     wfifo_cmap;
  49         u32     cport_rdwr;
  50         u32     port_cfg;
  51         u32     fpgaport_rst;   /* 0x80 */
  52         u32     __padding1;
  53         u32     fifo_cfg;
  54         u32     protport_default;
  55         u32     prot_rule_addr; /* 0x90 */
  56         u32     prot_rule_id;
  57         u32     prot_rule_data;
  58         u32     prot_rule_rdwr;
  59         u32     __padding2[3];
  60         u32     mp_priority;    /* 0xac */
  61         u32     mp_weight0;     /* 0xb0 */
  62         u32     mp_weight1;
  63         u32     mp_weight2;
  64         u32     mp_weight3;
  65         u32     mp_pacing0;     /* 0xc0 */
  66         u32     mp_pacing1;
  67         u32     mp_pacing2;
  68         u32     mp_pacing3;
  69         u32     mp_threshold0;  /* 0xd0 */
  70         u32     mp_threshold1;
  71         u32     mp_threshold2;
  72         u32     __padding3[29];
  73         u32     phy_ctrl0;      /* 0x150 */
  74         u32     phy_ctrl1;
  75         u32     phy_ctrl2;
  76 };
  77
  78 /* SDRAM configuration structure for the SPL. */
  79 struct socfpga_sdram_config {
  80         u32     ctrl_cfg;
  81         u32     dram_timing1;
  82         u32     dram_timing2;
  83         u32     dram_timing3;
  84         u32     dram_timing4;
  85         u32     lowpwr_timing;
  86         u32     dram_odt;
  87         u32     extratime1;
  88         u32     dram_addrw;
  89         u32     dram_if_width;
  90         u32     dram_dev_width;
  91         u32     dram_intr;
  92         u32     lowpwr_eq;
  93         u32     static_cfg;
  94         u32     ctrl_width;
  95         u32     cport_width;
  96         u32     cport_wmap;
  97         u32     cport_rmap;
  98         u32     rfifo_cmap;
  99         u32     wfifo_cmap;
 100         u32     cport_rdwr;
 101         u32     port_cfg;
 102         u32     fpgaport_rst;
 103         u32     fifo_cfg;
 104         u32     mp_priority;
 105         u32     mp_weight0;
 106         u32     mp_weight1;
 107         u32     mp_weight2;
 108         u32     mp_weight3;
 109         u32     mp_pacing0;
 110         u32     mp_pacing1;
 111         u32     mp_pacing2;
 112         u32     mp_pacing3;
 113         u32     mp_threshold0;
 114         u32     mp_threshold1;
 115         u32     mp_threshold2;
 116         u32     phy_ctrl0;
 117 };
 118
 119 struct socfpga_sdram_rw_mgr_config {
 120         u8      activate_0_and_1;
 121         u8      activate_0_and_1_wait1;
 122         u8      activate_0_and_1_wait2;
 123         u8      activate_1;
 124         u8      clear_dqs_enable;
 125         u8      guaranteed_read;
 126         u8      guaranteed_read_cont;
 127         u8      guaranteed_write;
 128         u8      guaranteed_write_wait0;
 129         u8      guaranteed_write_wait1;
 130         u8      guaranteed_write_wait2;
 131         u8      guaranteed_write_wait3;
 132         u8      idle;
 133         u8      idle_loop1;
 134         u8      idle_loop2;
 135         u8      init_reset_0_cke_0;
 136         u8      init_reset_1_cke_0;
 137         u8      lfsr_wr_rd_bank_0;
 138         u8      lfsr_wr_rd_bank_0_data;
 139         u8      lfsr_wr_rd_bank_0_dqs;
 140         u8      lfsr_wr_rd_bank_0_nop;
 141         u8      lfsr_wr_rd_bank_0_wait;
 142         u8      lfsr_wr_rd_bank_0_wl_1;
 143         u8      lfsr_wr_rd_dm_bank_0;
 144         u8      lfsr_wr_rd_dm_bank_0_data;
 145         u8      lfsr_wr_rd_dm_bank_0_dqs;
 146         u8      lfsr_wr_rd_dm_bank_0_nop;
 147         u8      lfsr_wr_rd_dm_bank_0_wait;
 148         u8      lfsr_wr_rd_dm_bank_0_wl_1;
 149         union {
 150                 u8      mrs0_dll_reset;
 151                 u8      mr_dll_reset;
 152         };
 153         union {
 154                 u8      mrs0_dll_reset_mirr;
 155                 u8      emr_ocd_enable;
 156         };
 157         union {
 158                 u8      mrs0_user;
 159                 u8      mr_user;
 160         };
 161         union {
 162                 u8      mrs0_user_mirr;
 163                 u8      mr_calib;
 164         };
 165         union {
 166                 u8      mrs1;
 167                 u8      emr;
 168         };
 169         union {
 170                 u8      mrs2;
 171                 u8      emr2;
 172         };
 173         union {
 174                 u8      mrs3;
 175                 u8      emr3;
 176         };
 177         u8      mrs1_mirr;
 178         u8      mrs2_mirr;
 179         u8      mrs3_mirr;
 180         u8      precharge_all;
 181         u8      read_b2b;
 182         u8      read_b2b_wait1;
 183         u8      read_b2b_wait2;
 184         union {
 185                 u8      refresh;
 186                 u8      refresh_all;
 187         };
 188         u8      rreturn;
 189         u8      sgle_read;
 190         union {
 191                 u8      zqcl;
 192                 u8      nop;
 193         };
 194
 195         u8      true_mem_data_mask_width;
 196         u8      mem_address_mirroring;
 197         u8      mem_data_mask_width;
 198         u8      mem_data_width;
 199         u8      mem_dq_per_read_dqs;
 200         u8      mem_dq_per_write_dqs;
 201         u8      mem_if_read_dqs_width;
 202         u8      mem_if_write_dqs_width;
 203         u8      mem_number_of_cs_per_dimm;
 204         u8      mem_number_of_ranks;
 205         u8      mem_virtual_groups_per_read_dqs;
 206         u8      mem_virtual_groups_per_write_dqs;
 207 };
 208
 209 struct socfpga_sdram_io_config {
 210         u16     delay_per_opa_tap;
 211         u8      delay_per_dchain_tap;
 212         u8      delay_per_dqs_en_dchain_tap;
 213         u8      dll_chain_length;
 214         u8      dqdqs_out_phase_max;
 215         u8      dqs_en_delay_max;
 216         u8      dqs_en_delay_offset;
 217         u8      dqs_en_phase_max;
 218         u8      dqs_in_delay_max;
 219         u8      dqs_in_reserve;
 220         u8      dqs_out_reserve;
 221         u8      io_in_delay_max;
 222         u8      io_out1_delay_max;
 223         u8      io_out2_delay_max;
 224         u8      shift_dqs_en_when_shift_dqs;
 225 };
 226
 227 struct socfpga_sdram_misc_config {
 228         u32     reg_file_init_seq_signature;
 229         u16     afi_clk_freq;
 230         u8      afi_rate_ratio;
 231         u8      calib_lfifo_offset;
 232         u8      calib_vfifo_offset;
 233         u8      enable_super_quick_calibration;
 234         u8      max_latency_count_width;
 235         u8      read_valid_fifo_size;
 236         u8      tinit_cntr0_val;
 237         u8      tinit_cntr1_val;
 238         u8      tinit_cntr2_val;
 239         u8      treset_cntr0_val;
 240         u8      treset_cntr1_val;
 241         u8      treset_cntr2_val;
 242 };
 243
 244 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
 245 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
 246 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
 247 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
 248 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
 249 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
 250 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
 251 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
 252 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
 253 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
 254 #define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
 255 #define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
 256 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
 257 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
 258 #define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
 259 #define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
 260 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
 261 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
 262 /* Register template: sdr::ctrlgrp::dramtiming1                            */
 263 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
 264 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
 265 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
 266 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
 267 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
 268 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
 269 #define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
 270 #define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
 271 #define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
 272 #define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
 273 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
 274 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
 275 /* Register template: sdr::ctrlgrp::dramtiming2                            */
 276 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
 277 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
 278 #define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
 279 #define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
 280 #define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
 281 #define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
 282 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
 283 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
 284 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
 285 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
 286 /* Register template: sdr::ctrlgrp::dramtiming3                            */
 287 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
 288 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
 289 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
 290 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
 291 #define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
 292 #define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
 293 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
 294 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
 295 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
 296 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
 297 /* Register template: sdr::ctrlgrp::dramtiming4                            */
 298 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
 299 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
 300 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
 301 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
 302 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
 303 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
 304 /* Register template: sdr::ctrlgrp::lowpwrtiming                           */
 305 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
 306 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
 307 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
 308 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
 309 /* Register template: sdr::ctrlgrp::dramaddrw                              */
 310 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
 311 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
 312 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
 313 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
 314 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
 315 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
 316 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
 317 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
 318 /* Register template: sdr::ctrlgrp::dramifwidth                            */
 319 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
 320 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
 321 /* Register template: sdr::ctrlgrp::dramdevwidth                           */
 322 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
 323 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
 324 /* Register template: sdr::ctrlgrp::dramintr                               */
 325 #define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
 326 #define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
 327 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
 328 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
 329 /* Register template: sdr::ctrlgrp::staticcfg                              */
 330 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
 331 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
 332 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
 333 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
 334 #define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
 335 #define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
 336 /* Register template: sdr::ctrlgrp::ctrlwidth                              */
 337 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
 338 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
 339 /* Register template: sdr::ctrlgrp::cportwidth                             */
 340 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
 341 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
 342 /* Register template: sdr::ctrlgrp::cportwmap                              */
 343 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
 344 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
 345 /* Register template: sdr::ctrlgrp::cportrmap                              */
 346 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
 347 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
 348 /* Register template: sdr::ctrlgrp::rfifocmap                              */
 349 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
 350 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
 351 /* Register template: sdr::ctrlgrp::wfifocmap                              */
 352 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
 353 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
 354 /* Register template: sdr::ctrlgrp::cportrdwr                              */
 355 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
 356 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
 357 /* Register template: sdr::ctrlgrp::portcfg                                */
 358 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
 359 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
 360 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
 361 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
 362 /* Register template: sdr::ctrlgrp::fifocfg                                */
 363 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
 364 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
 365 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
 366 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
 367 /* Register template: sdr::ctrlgrp::mppriority                             */
 368 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
 369 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
 370 /* Register template: sdr::ctrlgrp::mpweight::mpweight_0                   */
 371 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
 372 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
 373 /* Register template: sdr::ctrlgrp::mpweight::mpweight_1                   */
 374 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
 375 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
 376 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
 377 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
 378 /* Register template: sdr::ctrlgrp::mpweight::mpweight_2                   */
 379 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
 380 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
 381 /* Register template: sdr::ctrlgrp::mpweight::mpweight_3                   */
 382 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
 383 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
 384 /* Register template: sdr::ctrlgrp::mppacing::mppacing_0                   */
 385 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
 386 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
 387 /* Register template: sdr::ctrlgrp::mppacing::mppacing_1                   */
 388 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
 389 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
 390 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
 391 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
 392 /* Register template: sdr::ctrlgrp::mppacing::mppacing_2                   */
 393 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
 394 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
 395 /* Register template: sdr::ctrlgrp::mppacing::mppacing_3                   */
 396 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
 397 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
 398 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0       */
 399 #define \
 400 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
 401 #define  \
 402 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
 403 0xffffffff
 404 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1       */
 405 #define \
 406 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
 407 #define \
 408 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
 409 0xffffffff
 410 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2       */
 411 #define \
 412 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
 413 #define \
 414 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
 415 0x0000ffff
 416 /* Register template: sdr::ctrlgrp::remappriority                          */
 417 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
 418 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
 419 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0                     */
 420 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
 421 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
 422 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
 423  (((x) << 12) & 0xfffff000)
 424 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
 425  (((x) << 10) & 0x00000c00)
 426 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
 427  (((x) << 6) & 0x000000c0)
 428 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
 429  (((x) << 8) & 0x00000100)
 430 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
 431  (((x) << 9) & 0x00000200)
 432 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
 433  (((x) << 4) & 0x00000030)
 434 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
 435  (((x) << 2) & 0x0000000c)
 436 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
 437  (((x) << 0) & 0x00000003)
 438 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1                     */
 439 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
 440 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
 441  (((x) << 12) & 0xfffff000)
 442 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
 443  (((x) << 0) & 0x00000fff)
 444 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2                     */
 445 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
 446  (((x) << 0) & 0x00000fff)
 447 /* Register template: sdr::ctrlgrp::dramodt                                */
 448 #define SDR_CTRLGRP_DRAMODT_READ_LSB 4
 449 #define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
 450 #define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
 451 #define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
 452 /* Field instance: sdr::ctrlgrp::dramsts                                   */
 453 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
 454 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
 455 /* Register template: sdr::ctrlgrp::extratime1                             */
 456 #define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
 457 #define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
 458 #define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
 459
 460 /* SDRAM width macro for configuration with ECC */
 461 #define SDRAM_WIDTH_32BIT_WITH_ECC      40
 462 #define SDRAM_WIDTH_16BIT_WITH_ECC      24
 463
 464 #endif
 465 #endif /* _SOCFPGA_SDRAM_GEN5_H_ */