1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
7 #ifndef _RESET_MANAGER_S10_
8 #define _RESET_MANAGER_S10_
10 void reset_cpu(ulong addr);
11 int cpu_has_been_warmreset(void);
13 void socfpga_bridges_reset(int enable);
15 void socfpga_per_reset(u32 reset, int set);
16 void socfpga_per_reset_all(void);
18 struct socfpga_reset_manager {
43 u32 mpul2flushtimeout;
47 #define RSTMGR_MPUMODRST_CORE0 0
48 #define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
49 #define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
50 #define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
52 /* Watchdogs and MPU warm reset mask */
53 #define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
56 * Define a reset identifier, from which a permodrst bank ID
57 * and reset ID can be extracted using the subsequent macros
58 * RSTMGR_RESET() and RSTMGR_BANK().
60 #define RSTMGR_BANK_OFFSET 8
61 #define RSTMGR_BANK_MASK 0x7
62 #define RSTMGR_RESET_OFFSET 0
63 #define RSTMGR_RESET_MASK 0x1f
64 #define RSTMGR_DEFINE(_bank, _offset) \
65 ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
67 /* Extract reset ID from the reset identifier. */
68 #define RSTMGR_RESET(_reset) \
69 (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
71 /* Extract bank ID from the reset identifier. */
72 #define RSTMGR_BANK(_reset) \
73 (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
76 * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
82 #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
83 #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
84 #define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
85 #define RSTMGR_USB0 RSTMGR_DEFINE(1, 3)
86 #define RSTMGR_USB1 RSTMGR_DEFINE(1, 4)
87 #define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
88 #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
89 #define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8)
90 #define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9)
91 #define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10)
92 #define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11)
93 #define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12)
94 #define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13)
95 #define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15)
96 #define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
97 #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
98 #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
99 #define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
100 #define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
101 #define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2)
102 #define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3)
103 #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4)
104 #define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8)
105 #define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9)
106 #define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10)
107 #define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11)
108 #define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12)
109 #define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
110 #define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
111 #define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24)
112 #define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25)
113 #define RSTMGR_SDR RSTMGR_DEFINE(3, 6)
115 /* Create a human-readable reference to SoCFPGA reset. */
116 #define SOCFPGA_RESET(_name) RSTMGR_##_name
118 #endif /* _RESET_MANAGER_S10_ */