1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
6 #ifndef _RESET_MANAGER_GEN5_H_
7 #define _RESET_MANAGER_GEN5_H_
9 #include <dt-bindings/reset/altr,rst-mgr.h>
11 void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
12 void socfpga_bridges_reset(int enable);
14 struct socfpga_reset_manager {
29 * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
36 #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
37 #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
38 #define RSTMGR_NAND RSTMGR_DEFINE(1, 4)
39 #define RSTMGR_QSPI RSTMGR_DEFINE(1, 5)
40 #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6)
41 #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8)
42 #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16)
43 #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18)
44 #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19)
45 #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22)
46 #define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
47 #define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
49 #endif /* _RESET_MANAGER_GEN5_H_ */