1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
6 #ifndef _RESET_MANAGER_H_
7 #define _RESET_MANAGER_H_
9 phys_addr_t socfpga_get_rstmgr_addr(void);
11 void reset_cpu(ulong addr);
13 void socfpga_per_reset(u32 reset, int set);
14 void socfpga_per_reset_all(void);
16 #define RSTMGR_CTRL_SWCOLDRSTREQ_LSB 0
17 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
20 * Define a reset identifier, from which a permodrst bank ID
21 * and reset ID can be extracted using the subsequent macros
22 * RSTMGR_RESET() and RSTMGR_BANK().
24 #define RSTMGR_BANK_OFFSET 8
25 #define RSTMGR_BANK_MASK 0x7
26 #define RSTMGR_RESET_OFFSET 0
27 #define RSTMGR_RESET_MASK 0x1f
28 #define RSTMGR_DEFINE(_bank, _offset) \
29 ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
31 /* Extract reset ID from the reset identifier. */
32 #define RSTMGR_RESET(_reset) \
33 (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
35 /* Extract bank ID from the reset identifier. */
36 #define RSTMGR_BANK(_reset) \
37 (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
39 /* Create a human-readable reference to SoCFPGA reset. */
40 #define SOCFPGA_RESET(_name) RSTMGR_##_name
42 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
43 #include <asm/arch/reset_manager_gen5.h>
44 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
45 #include <asm/arch/reset_manager_arria10.h>
46 #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
47 #include <asm/arch/reset_manager_soc64.h>
50 #endif /* _RESET_MANAGER_H_ */