1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
7 #ifndef _FPGA_MANAGER_GEN5_H_
8 #define _FPGA_MANAGER_GEN5_H_
10 #include <linux/bitops.h>
11 #define FPGAMGRREGS_STAT_MODE_MASK 0x7
12 #define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
13 #define FPGAMGRREGS_STAT_MSEL_LSB 3
15 #define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9)
16 #define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8)
17 #define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2)
18 #define FPGAMGRREGS_CTRL_NCE_MASK BIT(1)
19 #define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
20 #define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
22 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3)
23 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2)
24 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1)
25 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
28 #define FPGAMGRREGS_MODE_FPGAOFF 0x0
29 #define FPGAMGRREGS_MODE_RESETPHASE 0x1
30 #define FPGAMGRREGS_MODE_CFGPHASE 0x2
31 #define FPGAMGRREGS_MODE_INITPHASE 0x3
32 #define FPGAMGRREGS_MODE_USERMODE 0x4
33 #define FPGAMGRREGS_MODE_UNKNOWN 0x5
37 struct socfpga_fpga_manager {
38 /* FPGA Manager Module */
46 u32 _pad_0x1c_0x82c[517];
48 /* Configuration Monitor (MON) Registers */
49 u32 gpio_inten; /* 0x830 */
51 u32 gpio_inttype_level;
52 u32 gpio_int_polarity;
53 u32 gpio_intstatus; /* 0x840 */
54 u32 gpio_raw_intstatus;
57 u32 gpio_ext_porta; /* 0x850 */
58 u32 _pad_0x854_0x85c[3];
59 u32 gpio_1s_sync; /* 0x860 */
60 u32 _pad_0x864_0x868[2];
62 u32 gpio_config_reg2; /* 0x870 */
66 #endif /* __ASSEMBLY__ */
68 #endif /* _FPGA_MANAGER_GEN5_H_ */