1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
7 #ifndef _FPGA_MANAGER_GEN5_H_
8 #define _FPGA_MANAGER_GEN5_H_
10 #define FPGAMGRREGS_STAT_MODE_MASK 0x7
11 #define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
12 #define FPGAMGRREGS_STAT_MSEL_LSB 3
14 #define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9)
15 #define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8)
16 #define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2)
17 #define FPGAMGRREGS_CTRL_NCE_MASK BIT(1)
18 #define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
19 #define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
21 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3)
22 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2)
23 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1)
24 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
27 #define FPGAMGRREGS_MODE_FPGAOFF 0x0
28 #define FPGAMGRREGS_MODE_RESETPHASE 0x1
29 #define FPGAMGRREGS_MODE_CFGPHASE 0x2
30 #define FPGAMGRREGS_MODE_INITPHASE 0x3
31 #define FPGAMGRREGS_MODE_USERMODE 0x4
32 #define FPGAMGRREGS_MODE_UNKNOWN 0x5
36 struct socfpga_fpga_manager {
37 /* FPGA Manager Module */
45 u32 _pad_0x1c_0x82c[517];
47 /* Configuration Monitor (MON) Registers */
48 u32 gpio_inten; /* 0x830 */
50 u32 gpio_inttype_level;
51 u32 gpio_int_polarity;
52 u32 gpio_intstatus; /* 0x840 */
53 u32 gpio_raw_intstatus;
56 u32 gpio_ext_porta; /* 0x850 */
57 u32 _pad_0x854_0x85c[3];
58 u32 gpio_1s_sync; /* 0x860 */
59 u32 _pad_0x864_0x868[2];
61 u32 gpio_config_reg2; /* 0x870 */
65 #endif /* __ASSEMBLY__ */
67 #endif /* _FPGA_MANAGER_GEN5_H_ */