1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
10 struct socfpga_firwall_l4_per {
42 struct socfpga_firwall_l4_sys {
43 u32 _pad_0x00; /* 0x00 */
47 u32 emac0tx_ecc; /* 0x10 */
51 u32 emac2tx_ecc; /* 0x20 */
55 u32 nand_read_ecc; /* 0x30 */
59 u32 sdmmc_ecc; /* 0x40 */
63 u32 _pad_0x50; /* 0x50 */
67 u32 osc0_timer; /* 0x60 */
71 u32 watchdog2; /* 0x70 */
75 #define FIREWALL_L4_DISABLE_ALL (BIT(0) | BIT(24) | BIT(16))
76 #define FIREWALL_BRIDGE_DISABLE_ALL (~0)
78 /* Cache coherency unit (CCU) registers */
79 #define CCU_CPU0_MPRT_ADBASE_DDRREG 0x4400
80 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE0 0x45c0
81 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A 0x45e0
82 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B 0x4600
83 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C 0x4620
84 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D 0x4640
85 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E 0x4660
87 #define CCU_CPU0_MPRT_ADMASK_MEM_RAM0 0x4688
89 #define CCU_IOM_MPRT_ADBASE_MEMSPACE0 0x18560
90 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1A 0x18580
91 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1B 0x185a0
92 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1C 0x185c0
93 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1D 0x185e0
94 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1E 0x18600
96 #define CCU_IOM_MPRT_ADMASK_MEM_RAM0 0x18628
98 #define CCU_ADMASK_P_MASK BIT(0)
99 #define CCU_ADMASK_NS_MASK BIT(1)
101 #define CCU_ADBASE_DI_MASK BIT(4)
103 #define CCU_REG_ADDR(reg) \
104 (SOCFPGA_CCU_ADDRESS + (reg))
106 /* Firewall MPU DDR SCR registers */
107 #define FW_MPU_DDR_SCR_EN 0x00
108 #define FW_MPU_DDR_SCR_EN_SET 0x04
109 #define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT 0x18
110 #define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c
111 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98
112 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
114 #define MPUREGION0_ENABLE BIT(0)
115 #define NONMPUREGION0_ENABLE BIT(8)
117 #define FW_MPU_DDR_SCR_WRITEL(data, reg) \
118 writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg))
120 void firewall_setup(void);
122 #endif /* _FIREWALL_H_ */