arch/arm/mach-socfpga/include/mach/clock_manager_s10.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef _CLOCK_MANAGER_S10_
   8 #define _CLOCK_MANAGER_S10_
   9
  10 #include <asm/arch/clock_manager_soc64.h>
  11 #include <linux/bitops.h>
  12
  13 /* Clock speed accessors */
  14 unsigned long cm_get_mpu_clk_hz(void);
  15 unsigned long cm_get_sdram_clk_hz(void);
  16 unsigned int cm_get_l4_sp_clk_hz(void);
  17 unsigned int cm_get_mmc_controller_clk_hz(void);
  18 unsigned int cm_get_qspi_controller_clk_hz(void);
  19 unsigned int cm_get_spi_controller_clk_hz(void);
  20
  21 struct cm_config {
  22         /* main group */
  23         u32 main_pll_mpuclk;
  24         u32 main_pll_nocclk;
  25         u32 main_pll_cntr2clk;
  26         u32 main_pll_cntr3clk;
  27         u32 main_pll_cntr4clk;
  28         u32 main_pll_cntr5clk;
  29         u32 main_pll_cntr6clk;
  30         u32 main_pll_cntr7clk;
  31         u32 main_pll_cntr8clk;
  32         u32 main_pll_cntr9clk;
  33         u32 main_pll_nocdiv;
  34         u32 main_pll_pllglob;
  35         u32 main_pll_fdbck;
  36         u32 main_pll_pllc0;
  37         u32 main_pll_pllc1;
  38         u32 spare;
  39
  40         /* peripheral group */
  41         u32 per_pll_cntr2clk;
  42         u32 per_pll_cntr3clk;
  43         u32 per_pll_cntr4clk;
  44         u32 per_pll_cntr5clk;
  45         u32 per_pll_cntr6clk;
  46         u32 per_pll_cntr7clk;
  47         u32 per_pll_cntr8clk;
  48         u32 per_pll_cntr9clk;
  49         u32 per_pll_emacctl;
  50         u32 per_pll_gpiodiv;
  51         u32 per_pll_pllglob;
  52         u32 per_pll_fdbck;
  53         u32 per_pll_pllc0;
  54         u32 per_pll_pllc1;
  55
  56         /* incoming clock */
  57         u32 hps_osc_clk_hz;
  58         u32 fpga_clk_hz;
  59 };
  60
  61 void cm_basic_init(const struct cm_config * const cfg);
  62
  63 /* Control status */
  64 #define CLKMGR_S10_CTRL                                 0x00
  65 #define CLKMGR_S10_STAT                                 0x04
  66 #define CLKMGR_S10_INTRCLR                              0x14
  67 /* Mainpll group */
  68 #define CLKMGR_S10_MAINPLL_EN                           0x30
  69 #define CLKMGR_S10_MAINPLL_BYPASS                       0x3c
  70 #define CLKMGR_S10_MAINPLL_MPUCLK                       0x48
  71 #define CLKMGR_S10_MAINPLL_NOCCLK                       0x4c
  72 #define CLKMGR_S10_MAINPLL_CNTR2CLK                     0x50
  73 #define CLKMGR_S10_MAINPLL_CNTR3CLK                     0x54
  74 #define CLKMGR_S10_MAINPLL_CNTR4CLK                     0x58
  75 #define CLKMGR_S10_MAINPLL_CNTR5CLK                     0x5c
  76 #define CLKMGR_S10_MAINPLL_CNTR6CLK                     0x60
  77 #define CLKMGR_S10_MAINPLL_CNTR7CLK                     0x64
  78 #define CLKMGR_S10_MAINPLL_CNTR8CLK                     0x68
  79 #define CLKMGR_S10_MAINPLL_CNTR9CLK                     0x6c
  80 #define CLKMGR_S10_MAINPLL_NOCDIV                       0x70
  81 #define CLKMGR_S10_MAINPLL_PLLGLOB                      0x74
  82 #define CLKMGR_S10_MAINPLL_FDBCK                        0x78
  83 #define CLKMGR_S10_MAINPLL_MEMSTAT                      0x80
  84 #define CLKMGR_S10_MAINPLL_PLLC0                        0x84
  85 #define CLKMGR_S10_MAINPLL_PLLC1                        0x88
  86 #define CLKMGR_S10_MAINPLL_VCOCALIB                     0x8c
  87 /* Periphpll group */
  88 #define CLKMGR_S10_PERPLL_EN                            0xa4
  89 #define CLKMGR_S10_PERPLL_BYPASS                        0xb0
  90 #define CLKMGR_S10_PERPLL_CNTR2CLK                      0xbc
  91 #define CLKMGR_S10_PERPLL_CNTR3CLK                      0xc0
  92 #define CLKMGR_S10_PERPLL_CNTR4CLK                      0xc4
  93 #define CLKMGR_S10_PERPLL_CNTR5CLK                      0xc8
  94 #define CLKMGR_S10_PERPLL_CNTR6CLK                      0xcc
  95 #define CLKMGR_S10_PERPLL_CNTR7CLK                      0xd0
  96 #define CLKMGR_S10_PERPLL_CNTR8CLK                      0xd4
  97 #define CLKMGR_S10_PERPLL_CNTR9CLK                      0xd8
  98 #define CLKMGR_S10_PERPLL_EMACCTL                       0xdc
  99 #define CLKMGR_S10_PERPLL_GPIODIV                       0xe0
 100 #define CLKMGR_S10_PERPLL_PLLGLOB                       0xe4
 101 #define CLKMGR_S10_PERPLL_FDBCK                         0xe8
 102 #define CLKMGR_S10_PERPLL_MEMSTAT                       0xf0
 103 #define CLKMGR_S10_PERPLL_PLLC0                         0xf4
 104 #define CLKMGR_S10_PERPLL_PLLC1                         0xf8
 105 #define CLKMGR_S10_PERPLL_VCOCALIB                      0xfc
 106
 107 #define CLKMGR_STAT                                     CLKMGR_S10_STAT
 108 #define CLKMGR_INTER                                    CLKMGR_S10_INTER
 109 #define CLKMGR_PERPLL_EN                                CLKMGR_S10_PERPLL_EN
 110
 111
 112 #define CLKMGR_CTRL_SAFEMODE                            BIT(0)
 113 #define CLKMGR_BYPASS_MAINPLL_ALL                       0x00000007
 114 #define CLKMGR_BYPASS_PERPLL_ALL                        0x0000007f
 115
 116 #define CLKMGR_INTER_MAINPLLLOCKED_MASK                 0x00000001
 117 #define CLKMGR_INTER_PERPLLLOCKED_MASK                  0x00000002
 118 #define CLKMGR_INTER_MAINPLLLOST_MASK                   0x00000004
 119 #define CLKMGR_INTER_PERPLLLOST_MASK                    0x00000008
 120 #define CLKMGR_STAT_BUSY                                BIT(0)
 121 #define CLKMGR_STAT_MAINPLL_LOCKED                      BIT(8)
 122 #define CLKMGR_STAT_PERPLL_LOCKED                       BIT(9)
 123
 124 #define CLKMGR_PLLGLOB_PD_MASK                          0x00000001
 125 #define CLKMGR_PLLGLOB_RST_MASK                         0x00000002
 126 #define CLKMGR_PLLGLOB_VCO_PSRC_MASK                    0X3
 127 #define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET                  16
 128 #define CLKMGR_VCO_PSRC_EOSC1                           0
 129 #define CLKMGR_VCO_PSRC_INTOSC                          1
 130 #define CLKMGR_VCO_PSRC_F2S                             2
 131 #define CLKMGR_PLLGLOB_REFCLKDIV_MASK                   0X3f
 132 #define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET                 8
 133
 134 #define CLKMGR_CLKSRC_MASK                              0x7
 135 #define CLKMGR_CLKSRC_OFFSET                            16
 136 #define CLKMGR_CLKSRC_MAIN                              0
 137 #define CLKMGR_CLKSRC_PER                               1
 138 #define CLKMGR_CLKSRC_OSC1                              2
 139 #define CLKMGR_CLKSRC_INTOSC                            3
 140 #define CLKMGR_CLKSRC_FPGA                              4
 141 #define CLKMGR_CLKCNT_MSK                               0x7ff
 142
 143 #define CLKMGR_FDBCK_MDIV_MASK                          0xff
 144 #define CLKMGR_FDBCK_MDIV_OFFSET                        24
 145
 146 #define CLKMGR_PLLC0_DIV_MASK                           0xff
 147 #define CLKMGR_PLLC1_DIV_MASK                           0xff
 148 #define CLKMGR_PLLC0_EN_OFFSET                          27
 149 #define CLKMGR_PLLC1_EN_OFFSET                          24
 150
 151 #define CLKMGR_NOCDIV_L4MAIN_OFFSET                     0
 152 #define CLKMGR_NOCDIV_L4MPCLK_OFFSET                    8
 153 #define CLKMGR_NOCDIV_L4SPCLK_OFFSET                    16
 154 #define CLKMGR_NOCDIV_CSATCLK_OFFSET                    24
 155 #define CLKMGR_NOCDIV_CSTRACECLK_OFFSET                 26
 156 #define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET                  28
 157
 158 #define CLKMGR_NOCDIV_L4SPCLK_MASK                      0X3
 159 #define CLKMGR_NOCDIV_DIV1                              0
 160 #define CLKMGR_NOCDIV_DIV2                              1
 161 #define CLKMGR_NOCDIV_DIV4                              2
 162 #define CLKMGR_NOCDIV_DIV8                              3
 163 #define CLKMGR_CSPDBGCLK_DIV1                           0
 164 #define CLKMGR_CSPDBGCLK_DIV4                           1
 165
 166 #define CLKMGR_MSCNT_CONST                              200
 167 #define CLKMGR_MDIV_CONST                               6
 168 #define CLKMGR_HSCNT_CONST                              9
 169
 170 #define CLKMGR_VCOCALIB_MSCNT_MASK                      0xff
 171 #define CLKMGR_VCOCALIB_MSCNT_OFFSET                    9
 172 #define CLKMGR_VCOCALIB_HSCNT_MASK                      0xff
 173
 174 #define CLKMGR_EMACCTL_EMAC0SEL_OFFSET                  26
 175 #define CLKMGR_EMACCTL_EMAC1SEL_OFFSET                  27
 176 #define CLKMGR_EMACCTL_EMAC2SEL_OFFSET                  28
 177
 178 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK               0x00000020
 179
 180 #endif /* _CLOCK_MANAGER_S10_ */