1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2016-2017 Intel Corporation
6 #ifndef CLOCK_MANAGER_ARRIA10
7 #define CLOCK_MANAGER_ARRIA10
11 #include <linux/bitops.h>
13 /* Clock manager group */
14 #define CLKMGR_A10_CTRL 0x00
15 #define CLKMGR_A10_INTR 0x04
16 #define CLKMGR_A10_STAT 0x1c
18 #define CLKMGR_A10_MAINPLL_VCO0 0x40
19 #define CLKMGR_A10_MAINPLL_VCO1 0x44
20 #define CLKMGR_A10_MAINPLL_EN 0x48
21 #define CLKMGR_A10_MAINPLL_ENS 0x4c
22 #define CLKMGR_A10_MAINPLL_ENR 0x50
23 #define CLKMGR_A10_MAINPLL_BYPASS 0x54
24 #define CLKMGR_A10_MAINPLL_BYPASSS 0x58
25 #define CLKMGR_A10_MAINPLL_BYPASSR 0x5c
26 #define CLKMGR_A10_MAINPLL_MPUCLK 0x60
27 #define CLKMGR_A10_MAINPLL_NOCCLK 0x64
28 #define CLKMGR_A10_MAINPLL_CNTR2CLK 0x68
29 #define CLKMGR_A10_MAINPLL_CNTR3CLK 0x6c
30 #define CLKMGR_A10_MAINPLL_CNTR4CLK 0x70
31 #define CLKMGR_A10_MAINPLL_CNTR5CLK 0x74
32 #define CLKMGR_A10_MAINPLL_CNTR6CLK 0x78
33 #define CLKMGR_A10_MAINPLL_CNTR7CLK 0x7c
34 #define CLKMGR_A10_MAINPLL_CNTR8CLK 0x80
35 #define CLKMGR_A10_MAINPLL_CNTR9CLK 0x84
36 #define CLKMGR_A10_MAINPLL_CNTR15CLK 0x9c
37 #define CLKMGR_A10_MAINPLL_NOCDIV 0xa8
38 /* Peripheral PLL group */
39 #define CLKMGR_A10_PERPLL_VCO0 0xc0
40 #define CLKMGR_A10_PERPLL_VCO1 0xc4
41 #define CLKMGR_A10_PERPLL_EN 0xc8
42 #define CLKMGR_A10_PERPLL_ENS 0xcc
43 #define CLKMGR_A10_PERPLL_ENR 0xd0
44 #define CLKMGR_A10_PERPLL_BYPASS 0xd4
45 #define CLKMGR_A10_PERPLL_BYPASSS 0xd8
46 #define CLKMGR_A10_PERPLL_BYPASSR 0xdc
47 #define CLKMGR_A10_PERPLL_CNTR2CLK 0xe8
48 #define CLKMGR_A10_PERPLL_CNTR3CLK 0xec
49 #define CLKMGR_A10_PERPLL_CNTR4CLK 0xf0
50 #define CLKMGR_A10_PERPLL_CNTR5CLK 0xf4
51 #define CLKMGR_A10_PERPLL_CNTR6CLK 0xf8
52 #define CLKMGR_A10_PERPLL_CNTR7CLK 0xfc
53 #define CLKMGR_A10_PERPLL_CNTR8CLK 0x100
54 #define CLKMGR_A10_PERPLL_CNTR9CLK 0x104
55 #define CLKMGR_A10_PERPLL_EMACCTL 0x128
56 #define CLKMGR_A10_PERPLL_GPIOFIV 0x12c
58 #define CLKMGR_A10_ALTR_MPUCLK 0x140
59 #define CLKMGR_A10_ALTR_NOCCLK 0x144
61 #define CLKMGR_STAT CLKMGR_A10_STAT
62 #define CLKMGR_INTER CLKMGR_A10_INTER
63 #define CLKMGR_PERPLL_EN CLKMGR_A10_PERPLL_EN
65 #ifdef CONFIG_SPL_BUILD
66 int cm_basic_init(const void *blob);
69 #include <linux/bitops.h>
70 unsigned int cm_get_l4_sp_clk_hz(void);
71 unsigned long cm_get_mpu_clk_hz(void);
73 unsigned int cm_get_qspi_controller_clk_hz(void);
75 #endif /* __ASSEMBLY__ */
77 #define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
78 CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
81 #define CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
82 #define CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
83 #define CLKMGR_MAINPLL_VCO0_RESET 0x00010053
84 #define CLKMGR_MAINPLL_VCO1_RESET 0x00010001
85 #define CLKMGR_PERPLL_VCO0_RESET 0x00010053
86 #define CLKMGR_PERPLL_VCO1_RESET 0x00010001
87 #define CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0
88 #define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
89 #define CLKMGR_MAINPLL_VCO0_PSRC_F2S 0x2
90 #define CLKMGR_PERPLL_VCO0_PSRC_EOSC 0x0
91 #define CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC 0x1
92 #define CLKMGR_PERPLL_VCO0_PSRC_F2S 0x2
93 #define CLKMGR_PERPLL_VCO0_PSRC_MAIN 0x3
96 #define CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK BIT(6)
97 #define CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK BIT(7)
98 #define CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK BIT(8)
99 #define CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK BIT(9)
100 #define CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK BIT(17)
101 #define CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK BIT(0)
102 #define CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK BIT(1)
103 #define CLKMGR_MAINPLL_VCO0_EN_SET_MSK BIT(2)
104 #define CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK BIT(3)
105 #define CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK BIT(4)
106 #define CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK BIT(0)
107 #define CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK BIT(1)
108 #define CLKMGR_PERPLL_VCO0_EN_SET_MSK BIT(2)
109 #define CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK BIT(3)
110 #define CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK BIT(4)
111 #define CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK BIT(0)
112 #define CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK BIT(1)
113 #define CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK BIT(2)
114 #define CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK BIT(3)
115 #define CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK BIT(8)
116 #define CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK BIT(9)
117 #define CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK BIT(10)
118 #define CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK BIT(11)
119 #define CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK BIT(0)
120 #define CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK 0x00000300
121 #define CLKMGR_PERPLL_EN_RESET 0x00000f7f
122 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
123 #define CLKMGR_MAINPLL_VCO0_PSRC_MSK 0x00000003
124 #define CLKMGR_MAINPLL_VCO1_NUMER_MSK 0x00001fff
125 #define CLKMGR_MAINPLL_VCO1_DENOM_MSK 0x0000003f
126 #define CLKMGR_MAINPLL_CNTRCLK_MSK 0x000003ff
127 #define CLKMGR_PERPLL_VCO0_PSRC_MSK 0x00000003
128 #define CLKMGR_PERPLL_VCO1_NUMER_MSK 0x00001fff
129 #define CLKMGR_PERPLL_VCO1_DENOM_MSK 0x0000003f
130 #define CLKMGR_PERPLL_CNTRCLK_MSK 0x000003ff
131 #define CLKMGR_MAINPLL_MPUCLK_SRC_MSK 0x00000007
132 #define CLKMGR_MAINPLL_MPUCLK_CNT_MSK 0x000003ff
133 #define CLKMGR_MAINPLL_MPUCLK_SRC_MAIN 0
134 #define CLKMGR_MAINPLL_MPUCLK_SRC_PERI 1
135 #define CLKMGR_MAINPLL_MPUCLK_SRC_OSC1 2
136 #define CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC 3
137 #define CLKMGR_MAINPLL_MPUCLK_SRC_FPGA 4
138 #define CLKMGR_MAINPLL_NOCDIV_MSK 0x00000003
139 #define CLKMGR_MAINPLL_NOCCLK_CNT_MSK 0x000003ff
140 #define CLKMGR_MAINPLL_NOCCLK_SRC_MSK 0x00000007
141 #define CLKMGR_MAINPLL_NOCCLK_SRC_MAIN 0
142 #define CLKMGR_MAINPLL_NOCCLK_SRC_PERI 1
143 #define CLKMGR_MAINPLL_NOCCLK_SRC_OSC1 2
144 #define CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC 3
145 #define CLKMGR_MAINPLL_NOCCLK_SRC_FPGA 4
147 #define CLKMGR_PERPLLGRP_SRC_MSK 0x00000007
148 #define CLKMGR_PERPLLGRP_SRC_MAIN 0
149 #define CLKMGR_PERPLLGRP_SRC_PERI 1
150 #define CLKMGR_PERPLLGRP_SRC_OSC1 2
151 #define CLKMGR_PERPLLGRP_SRC_INTOSC 3
152 #define CLKMGR_PERPLLGRP_SRC_FPGA 4
154 /* bit shifting macro */
155 #define CLKMGR_MAINPLL_VCO0_PSRC_LSB 8
156 #define CLKMGR_PERPLL_VCO0_PSRC_LSB 8
157 #define CLKMGR_MAINPLL_VCO1_DENOM_LSB 16
158 #define CLKMGR_PERPLL_VCO1_DENOM_LSB 16
159 #define CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB 16
160 #define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
161 #define CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0
162 #define CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8
163 #define CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16
164 #define CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24
165 #define CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26
166 #define CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28
167 #define CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16
168 #define CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB 16
169 #define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
170 #define CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16
171 #define CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB 16
172 #define CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16
173 #define CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16
174 #define CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16
175 #define CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16
176 #define CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16
177 #define CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16
178 #define CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26
179 #define CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27
180 #define CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28
182 /* PLL ramping work around */
183 #define CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ 900000000
184 #define CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ 300000000
185 #define CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ 100000000
186 #define CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ 33000000
188 #define CLKMGR_STAT_BUSY BIT(0)
190 #endif /* CLOCK_MANAGER_ARRIA10 */