1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2016-2017 Intel Corporation
6 #ifndef CLOCK_MANAGER_ARRIA10
7 #define CLOCK_MANAGER_ARRIA10
11 struct socfpga_clock_manager_main_pll {
38 struct socfpga_clock_manager_per_pll {
64 struct socfpga_clock_manager_altera {
73 struct socfpga_clock_manager {
84 u32 _pad_0x24_0x40[7];
86 struct socfpga_clock_manager_main_pll main_pll;
88 struct socfpga_clock_manager_per_pll per_pll;
89 struct socfpga_clock_manager_altera altera;
92 #ifdef CONFIG_SPL_BUILD
93 int cm_basic_init(const void *blob);
96 unsigned int cm_get_l4_sp_clk_hz(void);
97 unsigned long cm_get_mpu_clk_hz(void);
99 unsigned int cm_get_qspi_controller_clk_hz(void);
101 #endif /* __ASSEMBLER__ */
103 #define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
104 #define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
105 #define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
106 CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
109 #define CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
110 #define CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
111 #define CLKMGR_MAINPLL_VCO0_RESET 0x00010053
112 #define CLKMGR_MAINPLL_VCO1_RESET 0x00010001
113 #define CLKMGR_PERPLL_VCO0_RESET 0x00010053
114 #define CLKMGR_PERPLL_VCO1_RESET 0x00010001
115 #define CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0
116 #define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
117 #define CLKMGR_MAINPLL_VCO0_PSRC_F2S 0x2
118 #define CLKMGR_PERPLL_VCO0_PSRC_EOSC 0x0
119 #define CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC 0x1
120 #define CLKMGR_PERPLL_VCO0_PSRC_F2S 0x2
121 #define CLKMGR_PERPLL_VCO0_PSRC_MAIN 0x3
124 #define CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK BIT(6)
125 #define CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK BIT(7)
126 #define CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK BIT(8)
127 #define CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK BIT(9)
128 #define CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK BIT(17)
129 #define CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK BIT(0)
130 #define CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK BIT(1)
131 #define CLKMGR_MAINPLL_VCO0_EN_SET_MSK BIT(2)
132 #define CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK BIT(3)
133 #define CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK BIT(4)
134 #define CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK BIT(0)
135 #define CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK BIT(1)
136 #define CLKMGR_PERPLL_VCO0_EN_SET_MSK BIT(2)
137 #define CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK BIT(3)
138 #define CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK BIT(4)
139 #define CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK BIT(0)
140 #define CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK BIT(1)
141 #define CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK BIT(2)
142 #define CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK BIT(3)
143 #define CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK BIT(8)
144 #define CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK BIT(9)
145 #define CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK BIT(10)
146 #define CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK BIT(11)
147 #define CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK BIT(0)
148 #define CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK 0x00000300
149 #define CLKMGR_PERPLL_EN_RESET 0x00000f7f
150 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
151 #define CLKMGR_MAINPLL_VCO0_PSRC_MSK 0x00000003
152 #define CLKMGR_MAINPLL_VCO1_NUMER_MSK 0x00001fff
153 #define CLKMGR_MAINPLL_VCO1_DENOM_MSK 0x0000003f
154 #define CLKMGR_MAINPLL_CNTRCLK_MSK 0x000003ff
155 #define CLKMGR_PERPLL_VCO0_PSRC_MSK 0x00000003
156 #define CLKMGR_PERPLL_VCO1_NUMER_MSK 0x00001fff
157 #define CLKMGR_PERPLL_VCO1_DENOM_MSK 0x0000003f
158 #define CLKMGR_PERPLL_CNTRCLK_MSK 0x000003ff
159 #define CLKMGR_MAINPLL_MPUCLK_SRC_MSK 0x00000007
160 #define CLKMGR_MAINPLL_MPUCLK_CNT_MSK 0x000003ff
161 #define CLKMGR_MAINPLL_MPUCLK_SRC_MAIN 0
162 #define CLKMGR_MAINPLL_MPUCLK_SRC_PERI 1
163 #define CLKMGR_MAINPLL_MPUCLK_SRC_OSC1 2
164 #define CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC 3
165 #define CLKMGR_MAINPLL_MPUCLK_SRC_FPGA 4
166 #define CLKMGR_MAINPLL_NOCDIV_MSK 0x00000003
167 #define CLKMGR_MAINPLL_NOCCLK_CNT_MSK 0x000003ff
168 #define CLKMGR_MAINPLL_NOCCLK_SRC_MSK 0x00000007
169 #define CLKMGR_MAINPLL_NOCCLK_SRC_MAIN 0
170 #define CLKMGR_MAINPLL_NOCCLK_SRC_PERI 1
171 #define CLKMGR_MAINPLL_NOCCLK_SRC_OSC1 2
172 #define CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC 3
173 #define CLKMGR_MAINPLL_NOCCLK_SRC_FPGA 4
175 #define CLKMGR_PERPLLGRP_SRC_MSK 0x00000007
176 #define CLKMGR_PERPLLGRP_SRC_MAIN 0
177 #define CLKMGR_PERPLLGRP_SRC_PERI 1
178 #define CLKMGR_PERPLLGRP_SRC_OSC1 2
179 #define CLKMGR_PERPLLGRP_SRC_INTOSC 3
180 #define CLKMGR_PERPLLGRP_SRC_FPGA 4
182 /* bit shifting macro */
183 #define CLKMGR_MAINPLL_VCO0_PSRC_LSB 8
184 #define CLKMGR_PERPLL_VCO0_PSRC_LSB 8
185 #define CLKMGR_MAINPLL_VCO1_DENOM_LSB 16
186 #define CLKMGR_PERPLL_VCO1_DENOM_LSB 16
187 #define CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB 16
188 #define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
189 #define CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0
190 #define CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8
191 #define CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16
192 #define CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24
193 #define CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26
194 #define CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28
195 #define CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16
196 #define CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB 16
197 #define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
198 #define CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16
199 #define CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB 16
200 #define CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16
201 #define CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16
202 #define CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16
203 #define CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16
204 #define CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16
205 #define CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16
206 #define CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26
207 #define CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27
208 #define CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28
210 /* PLL ramping work around */
211 #define CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ 900000000
212 #define CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ 300000000
213 #define CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ 100000000
214 #define CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ 33000000
216 #define CLKMGR_STAT_BUSY BIT(0)
218 #endif /* CLOCK_MANAGER_ARRIA10 */