2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _CLOCK_MANAGER_H_
8 #define _CLOCK_MANAGER_H_
11 /* Clock speed accessors */
12 unsigned long cm_get_mpu_clk_hz(void);
13 unsigned long cm_get_sdram_clk_hz(void);
14 unsigned int cm_get_l4_sp_clk_hz(void);
15 unsigned int cm_get_mmc_controller_clk_hz(void);
16 unsigned int cm_get_qspi_controller_clk_hz(void);
17 unsigned int cm_get_spi_controller_clk_hz(void);
18 const unsigned int cm_get_osc_clk_hz(const int osc);
19 const unsigned int cm_get_f2s_per_ref_clk_hz(void);
20 const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
22 /* Clock configuration accessors */
23 const struct cm_config * const cm_get_default_config(void);
28 uint32_t main_vco_base;
33 uint32_t mainnandsdmmcclk;
34 uint32_t cfg2fuser0clk;
40 /* peripheral group */
41 uint32_t peri_vco_base;
45 uint32_t pernandsdmmcclk;
53 uint32_t sdram_vco_base;
60 uint32_t altera_grp_mpuclk;
63 void cm_basic_init(const struct cm_config * const cfg);
65 struct socfpga_clock_manager_main_pll {
80 u32 _pad_0x38_0x40[2];
83 struct socfpga_clock_manager_per_pll {
97 u32 _pad_0x34_0x40[3];
100 struct socfpga_clock_manager_sdr_pll {
111 struct socfpga_clock_manager_altera {
116 struct socfpga_clock_manager {
123 u32 _pad_0x18_0x3f[10];
124 struct socfpga_clock_manager_main_pll main_pll;
125 struct socfpga_clock_manager_per_pll per_pll;
126 struct socfpga_clock_manager_sdr_pll sdr_pll;
127 struct socfpga_clock_manager_altera altera;
128 u32 _pad_0xe8_0x200[70];
131 #define CLKMGR_CTRL_SAFEMODE (1 << 0)
132 #define CLKMGR_CTRL_SAFEMODE_OFFSET 0
134 #define CLKMGR_BYPASS_PERPLLSRC (1 << 4)
135 #define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4
136 #define CLKMGR_BYPASS_PERPLL (1 << 3)
137 #define CLKMGR_BYPASS_PERPLL_OFFSET 3
138 #define CLKMGR_BYPASS_SDRPLLSRC (1 << 2)
139 #define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2
140 #define CLKMGR_BYPASS_SDRPLL (1 << 1)
141 #define CLKMGR_BYPASS_SDRPLL_OFFSET 1
142 #define CLKMGR_BYPASS_MAINPLL (1 << 0)
143 #define CLKMGR_BYPASS_MAINPLL_OFFSET 0
145 #define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
146 #define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
147 #define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
148 #define CLKMGR_INTER_PERPLLLOST_MASK 0x00000010
149 #define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020
150 #define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008
152 #define CLKMGR_STAT_BUSY (1 << 0)
155 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0)
156 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0
157 #define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16
158 #define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000
159 #define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1)
160 #define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1
161 #define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3
162 #define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8
163 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
164 #define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2)
165 #define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2
166 #define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
167 #define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
169 #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0
170 #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff
172 #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0
173 #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff
175 #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0
176 #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff
178 #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0
179 #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff
181 #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0
182 #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff
184 #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0
185 #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff
187 #define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
188 #define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
189 #define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
190 #define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
191 #define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
192 #define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
194 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0
195 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003
196 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2
197 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c
198 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4
199 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070
200 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7
201 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380
203 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0
204 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003
205 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2
206 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c
208 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0
209 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007
211 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0)
212 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0
213 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1)
214 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1
215 #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
216 #define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0
217 #define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1
220 #define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16
221 #define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000
222 #define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3
223 #define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8
224 #define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
225 #define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22
226 #define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000
227 #define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
228 #define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
229 #define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22
230 #define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000
232 #define CLKMGR_VCO_SSRC_EOSC1 0x0
233 #define CLKMGR_VCO_SSRC_EOSC2 0x1
234 #define CLKMGR_VCO_SSRC_F2S 0x2
236 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0
237 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff
239 #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0
240 #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff
242 #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0
243 #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff
245 #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0
246 #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff
248 #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0
249 #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff
251 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0
252 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff
254 #define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
255 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100
257 #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6
258 #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0
259 #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9
260 #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00
261 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
262 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
263 #define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0
264 #define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007
266 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0
267 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff
269 #define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2
270 #define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c
271 #define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4
272 #define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030
273 #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
274 #define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0
275 #define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003
276 #define CLKMGR_SDMMC_CLK_SRC_F2S 0x0
277 #define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1
278 #define CLKMGR_SDMMC_CLK_SRC_PER 0x2
279 #define CLKMGR_QSPI_CLK_SRC_F2S 0x0
280 #define CLKMGR_QSPI_CLK_SRC_MAIN 0x1
281 #define CLKMGR_QSPI_CLK_SRC_PER 0x2
284 #define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16
285 #define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000
286 #define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3
287 #define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8
288 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24)
289 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24
290 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25
291 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
292 #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
293 #define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
294 #define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22
295 #define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000
297 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0
298 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
299 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9
300 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00
302 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0
303 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
304 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9
305 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00
307 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0
308 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
309 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9
310 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00
312 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0
313 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
314 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9
315 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00
317 #endif /* _CLOCK_MANAGER_H_ */