arch/arm/mach-socfpga/include/mach/base_addr_a10.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2014-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #ifndef _SOCFPGA_A10_BASE_HARDWARE_H_
   7 #define _SOCFPGA_A10_BASE_HARDWARE_H_
   8
   9 #define SOCFPGA_EMAC0_ADDRESS                   0xff800000
  10 #define SOCFPGA_EMAC1_ADDRESS                   0xff802000
  11 #define SOCFPGA_EMAC2_ADDRESS                   0xff804000
  12 #define SOCFPGA_SDMMC_ADDRESS                   0xff808000
  13 #define SOCFPGA_QSPIREGS_ADDRESS                0xff809000
  14 #define SOCFPGA_QSPIDATA_ADDRESS                0xffa00000
  15 #define SOCFPGA_UART1_ADDRESS                   0xffc02100
  16 #define SOCFPGA_HMC_MMR_IO48_ADDRESS            0xffcfa000
  17 #define SOCFPGA_FPGAMGRDATA_ADDRESS             0xffcfe400
  18 #define SOCFPGA_FPGAMGRREGS_ADDRESS             0xffd03000
  19 #define SOCFPGA_L4WD0_ADDRESS                   0xffd00200
  20 #define SOCFPGA_SYSMGR_ADDRESS                  0xffd06000
  21 #define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS     0xffd07000
  22 #define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS     0xffd07200
  23 #define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS 0xffd07300
  24 #define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS   0xffd07400
  25 #define SOCFPGA_DMANONSECURE_ADDRESS            0xffda0000
  26 #define SOCFPGA_DMASECURE_ADDRESS               0xffda1000
  27 #define SOCFPGA_MPUSCU_ADDRESS                  0xffffc000
  28 #define SOCFPGA_MPUL2_ADDRESS                   0xfffff000
  29 #define SOCFPGA_I2C0_ADDRESS                    0xffc02200
  30 #define SOCFPGA_I2C1_ADDRESS                    0xffc02300
  31 #define SOCFPGA_I2C2_ADDRESS                    0xffc02400
  32 #define SOCFPGA_I2C3_ADDRESS                    0xffc02500
  33 #define SOCFPGA_I2C4_ADDRESS                    0xffc02600
  34
  35 #define SOCFPGA_ECC_OCRAM_ADDRESS               0xff8c3000
  36 #define SOCFPGA_UART0_ADDRESS                   0xffc02000
  37 #define SOCFPGA_OSC1TIMER0_ADDRESS              0xffd00000
  38 #define SOCFPGA_OSC1TIMER1_ADDRESS              0xffd00100
  39 #define SOCFPGA_CLKMGR_ADDRESS                  0xffd04000
  40 #define SOCFPGA_RSTMGR_ADDRESS                  0xffd05000
  41
  42 #define SOCFPGA_SDR_ADDRESS                     0xffcfb000
  43 #define SOCFPGA_NOC_L4_PRIV_FLT_OFST            0xffd11000
  44 #define SOCFPGA_SDR_SCHEDULER_ADDRESS           0xffd12400
  45 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS      0xffd13200
  46 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS   0xffd13300
  47 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS         0xffd13400
  48 #define SOCFPGA_NOC_FW_H2F_SCR_OFST             0xffd13500
  49
  50 #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */