arch/arm/mach-socfpga/clock_manager_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2017 Intel Corporation
   4  */
   5
   6 #include <common.h>
   7 #include <fdtdec.h>
   8 #include <asm/io.h>
   9 #include <dm.h>
  10 #include <clk.h>
  11 #include <dm/device-internal.h>
  12 #include <asm/arch/clock_manager.h>
  13
  14 #ifdef CONFIG_SPL_BUILD
  15
  16 static u32 eosc1_hz;
  17 static u32 cb_intosc_hz;
  18 static u32 f2s_free_hz;
  19
  20 struct mainpll_cfg {
  21         u32 vco0_psrc;
  22         u32 vco1_denom;
  23         u32 vco1_numer;
  24         u32 mpuclk;
  25         u32 mpuclk_cnt;
  26         u32 mpuclk_src;
  27         u32 nocclk;
  28         u32 nocclk_cnt;
  29         u32 nocclk_src;
  30         u32 cntr2clk_cnt;
  31         u32 cntr3clk_cnt;
  32         u32 cntr4clk_cnt;
  33         u32 cntr5clk_cnt;
  34         u32 cntr6clk_cnt;
  35         u32 cntr7clk_cnt;
  36         u32 cntr7clk_src;
  37         u32 cntr8clk_cnt;
  38         u32 cntr9clk_cnt;
  39         u32 cntr9clk_src;
  40         u32 cntr15clk_cnt;
  41         u32 nocdiv_l4mainclk;
  42         u32 nocdiv_l4mpclk;
  43         u32 nocdiv_l4spclk;
  44         u32 nocdiv_csatclk;
  45         u32 nocdiv_cstraceclk;
  46         u32 nocdiv_cspdbclk;
  47 };
  48
  49 struct perpll_cfg {
  50         u32 vco0_psrc;
  51         u32 vco1_denom;
  52         u32 vco1_numer;
  53         u32 cntr2clk_cnt;
  54         u32 cntr2clk_src;
  55         u32 cntr3clk_cnt;
  56         u32 cntr3clk_src;
  57         u32 cntr4clk_cnt;
  58         u32 cntr4clk_src;
  59         u32 cntr5clk_cnt;
  60         u32 cntr5clk_src;
  61         u32 cntr6clk_cnt;
  62         u32 cntr6clk_src;
  63         u32 cntr7clk_cnt;
  64         u32 cntr8clk_cnt;
  65         u32 cntr8clk_src;
  66         u32 cntr9clk_cnt;
  67         u32 cntr9clk_src;
  68         u32 emacctl_emac0sel;
  69         u32 emacctl_emac1sel;
  70         u32 emacctl_emac2sel;
  71         u32 gpiodiv_gpiodbclk;
  72 };
  73
  74 struct strtou32 {
  75         const char *str;
  76         const u32 val;
  77 };
  78
  79 static const struct strtou32 mainpll_cfg_tab[] = {
  80         { "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) },
  81         { "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) },
  82         { "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) },
  83         { "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) },
  84         { "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) },
  85         { "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) },
  86         { "nocclk-src", offsetof(struct mainpll_cfg, nocclk_src) },
  87         { "cntr2clk-cnt", offsetof(struct mainpll_cfg, cntr2clk_cnt) },
  88         { "cntr3clk-cnt", offsetof(struct mainpll_cfg, cntr3clk_cnt) },
  89         { "cntr4clk-cnt", offsetof(struct mainpll_cfg, cntr4clk_cnt) },
  90         { "cntr5clk-cnt", offsetof(struct mainpll_cfg, cntr5clk_cnt) },
  91         { "cntr6clk-cnt", offsetof(struct mainpll_cfg, cntr6clk_cnt) },
  92         { "cntr7clk-cnt", offsetof(struct mainpll_cfg, cntr7clk_cnt) },
  93         { "cntr7clk-src", offsetof(struct mainpll_cfg, cntr7clk_src) },
  94         { "cntr8clk-cnt", offsetof(struct mainpll_cfg, cntr8clk_cnt) },
  95         { "cntr9clk-cnt", offsetof(struct mainpll_cfg, cntr9clk_cnt) },
  96         { "cntr9clk-src", offsetof(struct mainpll_cfg, cntr9clk_src) },
  97         { "cntr15clk-cnt", offsetof(struct mainpll_cfg, cntr15clk_cnt) },
  98         { "nocdiv-l4mainclk", offsetof(struct mainpll_cfg, nocdiv_l4mainclk) },
  99         { "nocdiv-l4mpclk", offsetof(struct mainpll_cfg, nocdiv_l4mpclk) },
 100         { "nocdiv-l4spclk", offsetof(struct mainpll_cfg, nocdiv_l4spclk) },
 101         { "nocdiv-csatclk", offsetof(struct mainpll_cfg, nocdiv_csatclk) },
 102         { "nocdiv-cstraceclk", offsetof(struct mainpll_cfg, nocdiv_cstraceclk) },
 103         { "nocdiv-cspdbgclk", offsetof(struct mainpll_cfg, nocdiv_cspdbclk) },
 104 };
 105
 106 static const struct strtou32 perpll_cfg_tab[] = {
 107         { "vco0-psrc", offsetof(struct perpll_cfg, vco0_psrc) },
 108         { "vco1-denom", offsetof(struct perpll_cfg, vco1_denom) },
 109         { "vco1-numer", offsetof(struct perpll_cfg, vco1_numer) },
 110         { "cntr2clk-cnt", offsetof(struct perpll_cfg, cntr2clk_cnt) },
 111         { "cntr2clk-src", offsetof(struct perpll_cfg, cntr2clk_src) },
 112         { "cntr3clk-cnt", offsetof(struct perpll_cfg, cntr3clk_cnt) },
 113         { "cntr3clk-src", offsetof(struct perpll_cfg, cntr3clk_src) },
 114         { "cntr4clk-cnt", offsetof(struct perpll_cfg, cntr4clk_cnt) },
 115         { "cntr4clk-src", offsetof(struct perpll_cfg, cntr4clk_src) },
 116         { "cntr5clk-cnt", offsetof(struct perpll_cfg, cntr5clk_cnt) },
 117         { "cntr5clk-src", offsetof(struct perpll_cfg, cntr5clk_src) },
 118         { "cntr6clk-cnt", offsetof(struct perpll_cfg, cntr6clk_cnt) },
 119         { "cntr6clk-src", offsetof(struct perpll_cfg, cntr6clk_src) },
 120         { "cntr7clk-cnt", offsetof(struct perpll_cfg, cntr7clk_cnt) },
 121         { "cntr8clk-cnt", offsetof(struct perpll_cfg, cntr8clk_cnt) },
 122         { "cntr8clk-src", offsetof(struct perpll_cfg, cntr8clk_src) },
 123         { "cntr9clk-cnt", offsetof(struct perpll_cfg, cntr9clk_cnt) },
 124         { "emacctl-emac0sel", offsetof(struct perpll_cfg, emacctl_emac0sel) },
 125         { "emacctl-emac1sel", offsetof(struct perpll_cfg, emacctl_emac1sel) },
 126         { "emacctl-emac2sel", offsetof(struct perpll_cfg, emacctl_emac2sel) },
 127         { "gpiodiv-gpiodbclk", offsetof(struct perpll_cfg, gpiodiv_gpiodbclk) },
 128 };
 129
 130 static const struct strtou32 alteragrp_cfg_tab[] = {
 131         { "nocclk", offsetof(struct mainpll_cfg, nocclk) },
 132         { "mpuclk", offsetof(struct mainpll_cfg, mpuclk) },
 133 };
 134
 135 struct strtopu32 {
 136         const char *str;
 137         u32 *p;
 138 };
 139
 140 const struct strtopu32 dt_to_val[] = {
 141         { "altera_arria10_hps_eosc1", &eosc1_hz },
 142         { "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz },
 143         { "altera_arria10_hps_f2h_free", &f2s_free_hz },
 144 };
 145
 146 static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_tab,
 147                         int cfg_tab_len, void *cfg)
 148 {
 149         int i;
 150         u32 val;
 151
 152         for (i = 0; i < cfg_tab_len; i++) {
 153                 if (fdtdec_get_int_array(blob, node, cfg_tab[i].str, &val, 1)) {
 154                         /* could not find required property */
 155                         return -EINVAL;
 156                 }
 157                 *(u32 *)(cfg + cfg_tab[i].val) = val;
 158         }
 159
 160         return 0;
 161 }
 162
 163 static int of_get_input_clks(const void *blob)
 164 {
 165         struct udevice *dev;
 166         struct clk clk;
 167         int i, ret;
 168
 169         for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) {
 170                 memset(&clk, 0, sizeof(clk));
 171
 172                 ret = uclass_get_device_by_name(UCLASS_CLK, dt_to_val[i].str,
 173                                                 &dev);
 174                 if (ret)
 175                         return ret;
 176
 177                 ret = clk_request(dev, &clk);
 178                 if (ret)
 179                         return ret;
 180
 181                 *dt_to_val[i].p = clk_get_rate(&clk);
 182         }
 183
 184         return 0;
 185 }
 186
 187 static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,
 188                           struct perpll_cfg *per_cfg)
 189 {
 190         int ret, node, child, len;
 191         const char *node_name;
 192
 193         ret = of_get_input_clks(blob);
 194         if (ret)
 195                 return ret;
 196
 197         node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK_INIT);
 198
 199         if (node < 0)
 200                 return -EINVAL;
 201
 202         child = fdt_first_subnode(blob, node);
 203
 204         if (child < 0)
 205                 return -EINVAL;
 206
 207         node_name = fdt_get_name(blob, child, &len);
 208
 209         while (node_name) {
 210                 if (!strcmp(node_name, "mainpll")) {
 211                         if (of_to_struct(blob, child, mainpll_cfg_tab,
 212                                          ARRAY_SIZE(mainpll_cfg_tab), main_cfg))
 213                                 return -EINVAL;
 214                 } else if (!strcmp(node_name, "perpll")) {
 215                         if (of_to_struct(blob, child, perpll_cfg_tab,
 216                                          ARRAY_SIZE(perpll_cfg_tab), per_cfg))
 217                                 return -EINVAL;
 218                 } else if (!strcmp(node_name, "alteragrp")) {
 219                         if (of_to_struct(blob, child, alteragrp_cfg_tab,
 220                                          ARRAY_SIZE(alteragrp_cfg_tab), main_cfg))
 221                                 return -EINVAL;
 222                 }
 223                 child = fdt_next_subnode(blob, child);
 224
 225                 if (child < 0)
 226                         break;
 227
 228                 node_name = fdt_get_name(blob, child, &len);
 229         }
 230
 231         return 0;
 232 }
 233
 234 /* calculate the intended main VCO frequency based on handoff */
 235 static unsigned int cm_calc_handoff_main_vco_clk_hz
 236                                         (struct mainpll_cfg *main_cfg)
 237 {
 238         unsigned int clk_hz;
 239
 240         /* Check main VCO clock source: eosc, intosc or f2s? */
 241         switch (main_cfg->vco0_psrc) {
 242         case CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
 243                 clk_hz = eosc1_hz;
 244                 break;
 245         case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
 246                 clk_hz = cb_intosc_hz;
 247                 break;
 248         case CLKMGR_MAINPLL_VCO0_PSRC_F2S:
 249                 clk_hz = f2s_free_hz;
 250                 break;
 251         default:
 252                 return 0;
 253         }
 254
 255         /* calculate the VCO frequency */
 256         clk_hz /= 1 + main_cfg->vco1_denom;
 257         clk_hz *= 1 + main_cfg->vco1_numer;
 258
 259         return clk_hz;
 260 }
 261
 262 /* calculate the intended periph VCO frequency based on handoff */
 263 static unsigned int cm_calc_handoff_periph_vco_clk_hz(
 264                 struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 265 {
 266         unsigned int clk_hz;
 267
 268         /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */
 269         switch (per_cfg->vco0_psrc) {
 270         case CLKMGR_PERPLL_VCO0_PSRC_EOSC:
 271                 clk_hz = eosc1_hz;
 272                 break;
 273         case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
 274                 clk_hz = cb_intosc_hz;
 275                 break;
 276         case CLKMGR_PERPLL_VCO0_PSRC_F2S:
 277                 clk_hz = f2s_free_hz;
 278                 break;
 279         case CLKMGR_PERPLL_VCO0_PSRC_MAIN:
 280                 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 281                 clk_hz /= main_cfg->cntr15clk_cnt;
 282                 break;
 283         default:
 284                 return 0;
 285         }
 286
 287         /* calculate the VCO frequency */
 288         clk_hz /= 1 + per_cfg->vco1_denom;
 289         clk_hz *= 1 + per_cfg->vco1_numer;
 290
 291         return clk_hz;
 292 }
 293
 294 /* calculate the intended MPU clock frequency based on handoff */
 295 static unsigned int cm_calc_handoff_mpu_clk_hz(struct mainpll_cfg *main_cfg,
 296                                                struct perpll_cfg *per_cfg)
 297 {
 298         unsigned int clk_hz;
 299
 300         /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
 301         switch (main_cfg->mpuclk_src) {
 302         case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN:
 303                 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 304                 clk_hz /= (main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK)
 305                            + 1;
 306                 break;
 307         case CLKMGR_MAINPLL_MPUCLK_SRC_PERI:
 308                 clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
 309                 clk_hz /= ((main_cfg->mpuclk >>
 310                            CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
 311                            CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1;
 312                 break;
 313         case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1:
 314                 clk_hz = eosc1_hz;
 315                 break;
 316         case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC:
 317                 clk_hz = cb_intosc_hz;
 318                 break;
 319         case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA:
 320                 clk_hz = f2s_free_hz;
 321                 break;
 322         default:
 323                 return 0;
 324         }
 325
 326         clk_hz /= main_cfg->mpuclk_cnt + 1;
 327         return clk_hz;
 328 }
 329
 330 /* calculate the intended NOC clock frequency based on handoff */
 331 static unsigned int cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg,
 332                                                struct perpll_cfg *per_cfg)
 333 {
 334         unsigned int clk_hz;
 335
 336         /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
 337         switch (main_cfg->nocclk_src) {
 338         case CLKMGR_MAINPLL_NOCCLK_SRC_MAIN:
 339                 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 340                 clk_hz /= (main_cfg->nocclk & CLKMGR_MAINPLL_NOCCLK_CNT_MSK)
 341                          + 1;
 342                 break;
 343         case CLKMGR_MAINPLL_NOCCLK_SRC_PERI:
 344                 clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
 345                 clk_hz /= ((main_cfg->nocclk >>
 346                            CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
 347                            CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1;
 348                 break;
 349         case CLKMGR_MAINPLL_NOCCLK_SRC_OSC1:
 350                 clk_hz = eosc1_hz;
 351                 break;
 352         case CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC:
 353                 clk_hz = cb_intosc_hz;
 354                 break;
 355         case CLKMGR_MAINPLL_NOCCLK_SRC_FPGA:
 356                 clk_hz = f2s_free_hz;
 357                 break;
 358         default:
 359                 return 0;
 360         }
 361
 362         clk_hz /= main_cfg->nocclk_cnt + 1;
 363         return clk_hz;
 364 }
 365
 366 /* return 1 if PLL ramp is required */
 367 static int cm_is_pll_ramp_required(int main0periph1,
 368                                    struct mainpll_cfg *main_cfg,
 369                                    struct perpll_cfg *per_cfg)
 370 {
 371         /* Check for main PLL */
 372         if (main0periph1 == 0) {
 373                 /*
 374                  * PLL ramp is not required if both MPU clock and NOC clock are
 375                  * not sourced from main PLL
 376                  */
 377                 if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
 378                     main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN)
 379                         return 0;
 380
 381                 /*
 382                  * PLL ramp is required if MPU clock is sourced from main PLL
 383                  * and MPU clock is over 900MHz (as advised by HW team)
 384                  */
 385                 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
 386                     (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
 387                      CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
 388                         return 1;
 389
 390                 /*
 391                  * PLL ramp is required if NOC clock is sourced from main PLL
 392                  * and NOC clock is over 300MHz (as advised by HW team)
 393                  */
 394                 if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN &&
 395                     (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
 396                      CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
 397                         return 2;
 398
 399         } else if (main0periph1 == 1) {
 400                 /*
 401                  * PLL ramp is not required if both MPU clock and NOC clock are
 402                  * not sourced from periph PLL
 403                  */
 404                 if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
 405                     main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI)
 406                         return 0;
 407
 408                 /*
 409                  * PLL ramp is required if MPU clock are source from periph PLL
 410                  * and MPU clock is over 900MHz (as advised by HW team)
 411                  */
 412                 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
 413                     (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
 414                      CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
 415                         return 1;
 416
 417                 /*
 418                  * PLL ramp is required if NOC clock are source from periph PLL
 419                  * and NOC clock is over 300MHz (as advised by HW team)
 420                  */
 421                 if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI &&
 422                     (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
 423                      CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
 424                         return 2;
 425         }
 426
 427         return 0;
 428 }
 429
 430 static u32 cm_calculate_numer(struct mainpll_cfg *main_cfg,
 431                               struct perpll_cfg *per_cfg,
 432                               u32 safe_hz, u32 clk_hz)
 433 {
 434         u32 cnt;
 435         u32 clk;
 436         u32 shift;
 437         u32 mask;
 438         u32 denom;
 439
 440         if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
 441                 cnt = main_cfg->mpuclk_cnt;
 442                 clk = main_cfg->mpuclk;
 443                 shift = 0;
 444                 mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK;
 445                 denom = main_cfg->vco1_denom;
 446         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
 447                 cnt = main_cfg->nocclk_cnt;
 448                 clk = main_cfg->nocclk;
 449                 shift = 0;
 450                 mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK;
 451                 denom = main_cfg->vco1_denom;
 452         } else if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
 453                 cnt = main_cfg->mpuclk_cnt;
 454                 clk = main_cfg->mpuclk;
 455                 shift = CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB;
 456                 mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK;
 457                 denom = per_cfg->vco1_denom;
 458         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
 459                 cnt = main_cfg->nocclk_cnt;
 460                 clk = main_cfg->nocclk;
 461                 shift = CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB;
 462                 mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK;
 463                 denom = per_cfg->vco1_denom;
 464         } else {
 465                 return 0;
 466         }
 467
 468         return (safe_hz / clk_hz) * (cnt + 1) * (((clk >> shift) & mask) + 1) *
 469                 (1 + denom) - 1;
 470 }
 471
 472 /*
 473  * Calculate the new PLL numerator which is based on existing DTS hand off and
 474  * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the
 475  * numerator while maintaining denominator as denominator will influence the
 476  * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final
 477  * value for numerator is minus with 1 to cater our register value
 478  * representation.
 479  */
 480 static unsigned int cm_calc_safe_pll_numer(int main0periph1,
 481                                            struct mainpll_cfg *main_cfg,
 482                                            struct perpll_cfg *per_cfg,
 483                                            unsigned int safe_hz)
 484 {
 485         unsigned int clk_hz = 0;
 486
 487         /* Check for main PLL */
 488         if (main0periph1 == 0) {
 489                 /* Check main VCO clock source: eosc, intosc or f2s? */
 490                 switch (main_cfg->vco0_psrc) {
 491                 case CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
 492                         clk_hz = eosc1_hz;
 493                         break;
 494                 case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
 495                         clk_hz = cb_intosc_hz;
 496                         break;
 497                 case CLKMGR_MAINPLL_VCO0_PSRC_F2S:
 498                         clk_hz = f2s_free_hz;
 499                         break;
 500                 default:
 501                         return 0;
 502                 }
 503         } else if (main0periph1 == 1) {
 504                 /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */
 505                 switch (per_cfg->vco0_psrc) {
 506                 case CLKMGR_PERPLL_VCO0_PSRC_EOSC:
 507                         clk_hz = eosc1_hz;
 508                         break;
 509                 case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
 510                         clk_hz = cb_intosc_hz;
 511                         break;
 512                 case CLKMGR_PERPLL_VCO0_PSRC_F2S:
 513                         clk_hz = f2s_free_hz;
 514                         break;
 515                 case CLKMGR_PERPLL_VCO0_PSRC_MAIN:
 516                         clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 517                         clk_hz /= main_cfg->cntr15clk_cnt;
 518                         break;
 519                 default:
 520                         return 0;
 521                 }
 522         } else {
 523                 return 0;
 524         }
 525
 526         return cm_calculate_numer(main_cfg, per_cfg, safe_hz, clk_hz);
 527 }
 528
 529 /* ramping the main PLL to final value */
 530 static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
 531                              struct perpll_cfg *per_cfg,
 532                              unsigned int pll_ramp_main_hz)
 533 {
 534         unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0;
 535
 536         /* find out the increment value */
 537         if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
 538                 clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
 539                 clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
 540         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
 541                 clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
 542                 clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
 543         }
 544
 545         /* execute the ramping here */
 546         for (clk_hz = pll_ramp_main_hz + clk_incr_hz;
 547              clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
 548                 writel((main_cfg->vco1_denom <<
 549                         CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 550                         cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
 551                         socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
 552                 mdelay(1);
 553                 cm_wait_for_lock(LOCKED_MASK);
 554         }
 555         writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 556                 main_cfg->vco1_numer,
 557                 socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
 558         mdelay(1);
 559         cm_wait_for_lock(LOCKED_MASK);
 560 }
 561
 562 /* ramping the periph PLL to final value */
 563 static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg,
 564                                struct perpll_cfg *per_cfg,
 565                                unsigned int pll_ramp_periph_hz)
 566 {
 567         unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0;
 568
 569         /* find out the increment value */
 570         if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
 571                 clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
 572                 clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
 573         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
 574                 clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
 575                 clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
 576         }
 577         /* execute the ramping here */
 578         for (clk_hz = pll_ramp_periph_hz + clk_incr_hz;
 579              clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
 580                 writel((per_cfg->vco1_denom <<
 581                               CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 582                               cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
 583                                                      clk_hz),
 584                               socfpga_get_clkmgr_addr() +
 585                               CLKMGR_A10_PERPLL_VCO1);
 586                 mdelay(1);
 587                 cm_wait_for_lock(LOCKED_MASK);
 588         }
 589         writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 590                       per_cfg->vco1_numer,
 591                       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 592         mdelay(1);
 593         cm_wait_for_lock(LOCKED_MASK);
 594 }
 595
 596 /*
 597  * Setup clocks while making no assumptions of the
 598  * previous state of the clocks.
 599  *
 600  * Start by being paranoid and gate all sw managed clocks
 601  *
 602  * Put all plls in bypass
 603  *
 604  * Put all plls VCO registers back to reset value (bgpwr dwn).
 605  *
 606  * Put peripheral and main pll src to reset value to avoid glitch.
 607  *
 608  * Delay 5 us.
 609  *
 610  * Deassert bg pwr dn and set numerator and denominator
 611  *
 612  * Start 7 us timer.
 613  *
 614  * set internal dividers
 615  *
 616  * Wait for 7 us timer.
 617  *
 618  * Enable plls
 619  *
 620  * Set external dividers while plls are locking
 621  *
 622  * Wait for pll lock
 623  *
 624  * Assert/deassert outreset all.
 625  *
 626  * Take all pll's out of bypass
 627  *
 628  * Clear safe mode
 629  *
 630  * set source main and peripheral clocks
 631  *
 632  * Ungate clocks
 633  */
 634
 635 static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 636 {
 637         unsigned int pll_ramp_main_hz = 0, pll_ramp_periph_hz = 0,
 638                 ramp_required;
 639
 640         /* gate off all mainpll clock excpet HW managed clock */
 641         writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
 642                 CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
 643                 socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_ENR);
 644
 645         /* now we can gate off the rest of the peripheral clocks */
 646         writel(0, socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_EN);
 647
 648         /* Put all plls in external bypass */
 649         writel(CLKMGR_MAINPLL_BYPASS_RESET,
 650                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSS);
 651         writel(CLKMGR_PERPLL_BYPASS_RESET,
 652                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSS);
 653
 654         /*
 655          * Put all plls VCO registers back to reset value.
 656          * Some code might have messed with them. At same time set the
 657          * desired clock source
 658          */
 659         writel(CLKMGR_MAINPLL_VCO0_RESET |
 660                CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK |
 661                (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB),
 662                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0);
 663
 664         writel(CLKMGR_PERPLL_VCO0_RESET |
 665                CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK |
 666                (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB),
 667                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0);
 668
 669         writel(CLKMGR_MAINPLL_VCO1_RESET,
 670                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
 671         writel(CLKMGR_PERPLL_VCO1_RESET,
 672                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 673
 674         /* clear the interrupt register status register */
 675         writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
 676                 CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
 677                 CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
 678                 CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
 679                 CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
 680                 CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK |
 681                 CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK |
 682                 CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK,
 683                 socfpga_get_clkmgr_addr() + CLKMGR_A10_INTR);
 684
 685         /* Program VCO Numerator and Denominator for main PLL */
 686         ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg);
 687         if (ramp_required) {
 688                 /* set main PLL to safe starting threshold frequency */
 689                 if (ramp_required == 1)
 690                         pll_ramp_main_hz = CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
 691                 else if (ramp_required == 2)
 692                         pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
 693
 694                 writel((main_cfg->vco1_denom <<
 695                         CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 696                         cm_calc_safe_pll_numer(0, main_cfg, per_cfg,
 697                                                pll_ramp_main_hz),
 698                         socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
 699         } else
 700                 writel((main_cfg->vco1_denom <<
 701                        CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 702                        main_cfg->vco1_numer,
 703                        socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
 704
 705         /* Program VCO Numerator and Denominator for periph PLL */
 706         ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg);
 707         if (ramp_required) {
 708                 /* set periph PLL to safe starting threshold frequency */
 709                 if (ramp_required == 1)
 710                         pll_ramp_periph_hz =
 711                                 CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
 712                 else if (ramp_required == 2)
 713                         pll_ramp_periph_hz =
 714                                 CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
 715
 716                 writel((per_cfg->vco1_denom <<
 717                         CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 718                         cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
 719                                                pll_ramp_periph_hz),
 720                         socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 721         } else
 722                 writel((per_cfg->vco1_denom <<
 723                         CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 724                         per_cfg->vco1_numer,
 725                         socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 726
 727         /* Wait for at least 5 us */
 728         udelay(5);
 729
 730         /* Now deassert BGPWRDN and PWRDN */
 731         clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
 732                      CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK |
 733                      CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK);
 734         clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0,
 735                      CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK |
 736                      CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
 737
 738         /* Wait for at least 7 us */
 739         udelay(7);
 740
 741         /* enable the VCO and disable the external regulator to PLL */
 742         writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) &
 743                 ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) |
 744                 CLKMGR_MAINPLL_VCO0_EN_SET_MSK,
 745                 socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0);
 746         writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0) &
 747                 ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) |
 748                 CLKMGR_PERPLL_VCO0_EN_SET_MSK,
 749                 socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0);
 750
 751         /* setup all the main PLL counter and clock source */
 752         writel(main_cfg->nocclk,
 753                socfpga_get_clkmgr_addr() + CLKMGR_A10_ALTR_NOCCLK);
 754         writel(main_cfg->mpuclk,
 755                socfpga_get_clkmgr_addr() + CLKMGR_A10_ALTR_MPUCLK);
 756
 757         /* main_emaca_clk divider */
 758         writel(main_cfg->cntr2clk_cnt,
 759                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR2CLK);
 760         /* main_emacb_clk divider */
 761         writel(main_cfg->cntr3clk_cnt,
 762                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR3CLK);
 763         /* main_emac_ptp_clk divider */
 764         writel(main_cfg->cntr4clk_cnt,
 765                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR4CLK);
 766         /* main_gpio_db_clk divider */
 767         writel(main_cfg->cntr5clk_cnt,
 768                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR5CLK);
 769         /* main_sdmmc_clk divider */
 770         writel(main_cfg->cntr6clk_cnt,
 771                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR6CLK);
 772         /* main_s2f_user0_clk divider */
 773         writel(main_cfg->cntr7clk_cnt |
 774                (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB),
 775                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR7CLK);
 776         /* main_s2f_user1_clk divider */
 777         writel(main_cfg->cntr8clk_cnt,
 778                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR8CLK);
 779         /* main_hmc_pll_clk divider */
 780         writel(main_cfg->cntr9clk_cnt |
 781                (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB),
 782                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR9CLK);
 783         /* main_periph_ref_clk divider */
 784         writel(main_cfg->cntr15clk_cnt,
 785                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR15CLK);
 786
 787         /* setup all the peripheral PLL counter and clock source */
 788         /* peri_emaca_clk divider */
 789         writel(per_cfg->cntr2clk_cnt |
 790                (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB),
 791                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR2CLK);
 792         /* peri_emacb_clk divider */
 793         writel(per_cfg->cntr3clk_cnt |
 794                (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB),
 795                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR3CLK);
 796         /* peri_emac_ptp_clk divider */
 797         writel(per_cfg->cntr4clk_cnt |
 798                (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB),
 799                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR4CLK);
 800         /* peri_gpio_db_clk divider */
 801         writel(per_cfg->cntr5clk_cnt |
 802                (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB),
 803                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR5CLK);
 804         /* peri_sdmmc_clk divider */
 805         writel(per_cfg->cntr6clk_cnt |
 806                (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB),
 807                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR6CLK);
 808         /* peri_s2f_user0_clk divider */
 809         writel(per_cfg->cntr7clk_cnt,
 810                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR7CLK);
 811         /* peri_s2f_user1_clk divider */
 812         writel(per_cfg->cntr8clk_cnt |
 813                (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB),
 814                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR8CLK);
 815         /* peri_hmc_pll_clk divider */
 816         writel(per_cfg->cntr9clk_cnt,
 817                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR9CLK);
 818
 819         /* setup all the external PLL counter */
 820         /* mpu wrapper / external divider */
 821         writel(main_cfg->mpuclk_cnt |
 822                (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB),
 823                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_MPUCLK);
 824         /* NOC wrapper / external divider */
 825         writel(main_cfg->nocclk_cnt |
 826                (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB),
 827                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_NOCCLK);
 828         /* NOC subclock divider such as l4 */
 829         writel(main_cfg->nocdiv_l4mainclk |
 830                (main_cfg->nocdiv_l4mpclk <<
 831                 CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) |
 832                (main_cfg->nocdiv_l4spclk <<
 833                 CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) |
 834                (main_cfg->nocdiv_csatclk <<
 835                 CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) |
 836                (main_cfg->nocdiv_cstraceclk <<
 837                 CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) |
 838                (main_cfg->nocdiv_cspdbclk <<
 839                 CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB),
 840                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_NOCDIV);
 841         /* gpio_db external divider */
 842         writel(per_cfg->gpiodiv_gpiodbclk,
 843                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_GPIOFIV);
 844
 845         /* setup the EMAC clock mux select */
 846         writel((per_cfg->emacctl_emac0sel <<
 847                 CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) |
 848                (per_cfg->emacctl_emac1sel <<
 849                 CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) |
 850                (per_cfg->emacctl_emac2sel <<
 851                 CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB),
 852                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_EMACCTL);
 853
 854         /* at this stage, check for PLL lock status */
 855         cm_wait_for_lock(LOCKED_MASK);
 856
 857         /*
 858          * after locking, but before taking out of bypass,
 859          * assert/deassert outresetall
 860          */
 861         /* assert mainpll outresetall */
 862         setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
 863                      CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
 864         /* assert perpll outresetall */
 865         setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0,
 866                      CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
 867         /* de-assert mainpll outresetall */
 868         clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
 869                      CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
 870         /* de-assert perpll outresetall */
 871         clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0,
 872                      CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
 873
 874         /* Take all PLLs out of bypass when boot mode is cleared. */
 875         /* release mainpll from bypass */
 876         writel(CLKMGR_MAINPLL_BYPASS_RESET,
 877                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSR);
 878         /* wait till Clock Manager is not busy */
 879         cm_wait_for_fsm();
 880
 881         /* release perpll from bypass */
 882         writel(CLKMGR_PERPLL_BYPASS_RESET,
 883                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSR);
 884         /* wait till Clock Manager is not busy */
 885         cm_wait_for_fsm();
 886
 887         /* clear boot mode */
 888         clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL,
 889                      CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
 890         /* wait till Clock Manager is not busy */
 891         cm_wait_for_fsm();
 892
 893         /* At here, we need to ramp to final value if needed */
 894         if (pll_ramp_main_hz != 0)
 895                 cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz);
 896         if (pll_ramp_periph_hz != 0)
 897                 cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz);
 898
 899         /* Now ungate non-hw-managed clocks */
 900         writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
 901                CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
 902                socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_ENS);
 903         writel(CLKMGR_PERPLL_EN_RESET,
 904                socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_ENS);
 905
 906         /* Clear the loss lock and slip bits as they might set during
 907         clock reconfiguration */
 908         writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
 909                CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
 910                CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
 911                CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
 912                CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
 913                CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK,
 914                socfpga_get_clkmgr_addr() + CLKMGR_A10_INTR);
 915
 916         return 0;
 917 }
 918
 919 static void cm_use_intosc(void)
 920 {
 921         setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL,
 922                      CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK);
 923 }
 924
 925 int cm_basic_init(const void *blob)
 926 {
 927         struct mainpll_cfg main_cfg;
 928         struct perpll_cfg per_cfg;
 929         int rval;
 930
 931         /* initialize to zero for use case of optional node */
 932         memset(&main_cfg, 0, sizeof(main_cfg));
 933         memset(&per_cfg, 0, sizeof(per_cfg));
 934
 935         rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg);
 936         if (rval)
 937                 return rval;
 938
 939         cm_use_intosc();
 940
 941         return cm_full_cfg(&main_cfg, &per_cfg);
 942 }
 943 #endif
 944
 945 static u32 cm_get_rate_dm(char *name)
 946 {
 947         struct uclass *uc;
 948         struct udevice *dev = NULL;
 949         struct clk clk = { 0 };
 950         ulong rate;
 951         int ret;
 952
 953         /* Device addresses start at 1 */
 954         ret = uclass_get(UCLASS_CLK, &uc);
 955         if (ret)
 956                 return 0;
 957
 958         ret = uclass_get_device_by_name(UCLASS_CLK, name, &dev);
 959         if (ret)
 960                 return 0;
 961
 962         ret = device_probe(dev);
 963         if (ret)
 964                 return 0;
 965
 966         ret = clk_request(dev, &clk);
 967         if (ret)
 968                 return 0;
 969
 970         rate = clk_get_rate(&clk);
 971
 972         clk_free(&clk);
 973
 974         return rate;
 975 }
 976
 977 static u32 cm_get_rate_dm_khz(char *name)
 978 {
 979         return cm_get_rate_dm(name) / 1000;
 980 }
 981
 982 unsigned long cm_get_mpu_clk_hz(void)
 983 {
 984         return cm_get_rate_dm("main_mpu_base_clk");
 985 }
 986
 987 unsigned int cm_get_qspi_controller_clk_hz(void)
 988 {
 989         return cm_get_rate_dm("qspi_clk");
 990 }
 991
 992 unsigned int cm_get_l4_sp_clk_hz(void)
 993 {
 994         return cm_get_rate_dm("l4_sp_clk");
 995 }
 996
 997 void cm_print_clock_quick_summary(void)
 998 {
 999         printf("MPU       %10d kHz\n", cm_get_rate_dm_khz("main_mpu_base_clk"));
1000         printf("MMC         %8d kHz\n", cm_get_rate_dm_khz("sdmmc_clk"));
1001         printf("QSPI        %8d kHz\n", cm_get_rate_dm_khz("qspi_clk"));
1002         printf("SPI         %8d kHz\n", cm_get_rate_dm_khz("spi_m_clk"));
1003         printf("EOSC1       %8d kHz\n", cm_get_rate_dm_khz("osc1"));
1004         printf("cb_intosc   %8d kHz\n", cm_get_rate_dm_khz("cb_intosc_ls_clk"));
1005         printf("f2s_free    %8d kHz\n", cm_get_rate_dm_khz("f2s_free_clk"));
1006         printf("Main VCO    %8d kHz\n", cm_get_rate_dm_khz("main_pll@40"));
1007         printf("NOC         %8d kHz\n", cm_get_rate_dm_khz("main_noc_base_clk"));
1008         printf("L4 Main     %8d kHz\n", cm_get_rate_dm_khz("l4_main_clk"));
1009         printf("L4 MP       %8d kHz\n", cm_get_rate_dm_khz("l4_mp_clk"));
1010         printf("L4 SP       %8d kHz\n", cm_get_rate_dm_khz("l4_sp_clk"));
1011         printf("L4 sys free %8d kHz\n", cm_get_rate_dm_khz("l4_sys_free_clk"));
1012 }