arch/arm/mach-socfpga/clock_manager_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2017 Intel Corporation
   4  */
   5
   6 #include <common.h>
   7 #include <fdtdec.h>
   8 #include <asm/io.h>
   9 #include <dm.h>
  10 #include <asm/arch/clock_manager.h>
  11
  12 static u32 eosc1_hz;
  13 static u32 cb_intosc_hz;
  14 static u32 f2s_free_hz;
  15 static u32 cm_l4_main_clk_hz;
  16 static u32 cm_l4_sp_clk_hz;
  17 static u32 cm_l4_mp_clk_hz;
  18 static u32 cm_l4_sys_free_clk_hz;
  19
  20 struct mainpll_cfg {
  21         u32 vco0_psrc;
  22         u32 vco1_denom;
  23         u32 vco1_numer;
  24         u32 mpuclk;
  25         u32 mpuclk_cnt;
  26         u32 mpuclk_src;
  27         u32 nocclk;
  28         u32 nocclk_cnt;
  29         u32 nocclk_src;
  30         u32 cntr2clk_cnt;
  31         u32 cntr3clk_cnt;
  32         u32 cntr4clk_cnt;
  33         u32 cntr5clk_cnt;
  34         u32 cntr6clk_cnt;
  35         u32 cntr7clk_cnt;
  36         u32 cntr7clk_src;
  37         u32 cntr8clk_cnt;
  38         u32 cntr9clk_cnt;
  39         u32 cntr9clk_src;
  40         u32 cntr15clk_cnt;
  41         u32 nocdiv_l4mainclk;
  42         u32 nocdiv_l4mpclk;
  43         u32 nocdiv_l4spclk;
  44         u32 nocdiv_csatclk;
  45         u32 nocdiv_cstraceclk;
  46         u32 nocdiv_cspdbclk;
  47 };
  48
  49 struct perpll_cfg {
  50         u32 vco0_psrc;
  51         u32 vco1_denom;
  52         u32 vco1_numer;
  53         u32 cntr2clk_cnt;
  54         u32 cntr2clk_src;
  55         u32 cntr3clk_cnt;
  56         u32 cntr3clk_src;
  57         u32 cntr4clk_cnt;
  58         u32 cntr4clk_src;
  59         u32 cntr5clk_cnt;
  60         u32 cntr5clk_src;
  61         u32 cntr6clk_cnt;
  62         u32 cntr6clk_src;
  63         u32 cntr7clk_cnt;
  64         u32 cntr8clk_cnt;
  65         u32 cntr8clk_src;
  66         u32 cntr9clk_cnt;
  67         u32 emacctl_emac0sel;
  68         u32 emacctl_emac1sel;
  69         u32 emacctl_emac2sel;
  70         u32 gpiodiv_gpiodbclk;
  71 };
  72
  73 struct alteragrp_cfg {
  74         u32 nocclk;
  75         u32 mpuclk;
  76 };
  77
  78 static const struct socfpga_clock_manager *clock_manager_base =
  79         (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
  80
  81 static int of_to_struct(const void *blob, int node, int cfg_len, void *cfg)
  82 {
  83         if (fdtdec_get_int_array(blob, node, "altr,of_reg_value",
  84                                  (u32 *)cfg, cfg_len)) {
  85                 /* could not find required property */
  86                 return -EINVAL;
  87         }
  88
  89         return 0;
  90 }
  91
  92 static int of_get_input_clks(const void *blob, int node, u32 *val)
  93 {
  94         *val = fdtdec_get_uint(blob, node, "clock-frequency", 0);
  95         if (!*val)
  96                 return -EINVAL;
  97
  98         return 0;
  99 }
 100
 101 static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,
 102                           struct perpll_cfg *per_cfg,
 103                           struct alteragrp_cfg *altrgrp_cfg)
 104 {
 105         int node, child, len;
 106         const char *node_name;
 107
 108         node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK);
 109         if (node < 0)
 110                 return -EINVAL;
 111
 112         child = fdt_first_subnode(blob, node);
 113         if (child < 0)
 114                 return -EINVAL;
 115
 116         child = fdt_first_subnode(blob, child);
 117         if (child < 0)
 118                 return -EINVAL;
 119
 120         node_name = fdt_get_name(blob, child, &len);
 121
 122         while (node_name) {
 123                 if (!strcmp(node_name, "osc1")) {
 124                         if (of_get_input_clks(blob, child, &eosc1_hz))
 125                                 return -EINVAL;
 126                 } else if (!strcmp(node_name, "cb_intosc_ls_clk")) {
 127                         if (of_get_input_clks(blob, child, &cb_intosc_hz))
 128                                 return -EINVAL;
 129                 } else if (!strcmp(node_name, "f2s_free_clk")) {
 130                         if (of_get_input_clks(blob, child, &f2s_free_hz))
 131                                 return -EINVAL;
 132                 } else if (!strcmp(node_name, "main_pll")) {
 133                         if (of_to_struct(blob, child,
 134                                          sizeof(*main_cfg)/sizeof(u32),
 135                                          main_cfg))
 136                                 return -EINVAL;
 137                 } else if (!strcmp(node_name, "periph_pll")) {
 138                         if (of_to_struct(blob, child,
 139                                          sizeof(*per_cfg)/sizeof(u32),
 140                                          per_cfg))
 141                                 return -EINVAL;
 142                 } else if (!strcmp(node_name, "altera")) {
 143                         if (of_to_struct(blob, child,
 144                                          sizeof(*altrgrp_cfg)/sizeof(u32),
 145                                          altrgrp_cfg))
 146                                 return -EINVAL;
 147
 148                         main_cfg->mpuclk = altrgrp_cfg->mpuclk;
 149                         main_cfg->nocclk = altrgrp_cfg->nocclk;
 150                 }
 151                 child = fdt_next_subnode(blob, child);
 152
 153                 if (child < 0)
 154                         break;
 155
 156                 node_name = fdt_get_name(blob, child, &len);
 157         }
 158
 159         return 0;
 160 }
 161
 162 /* calculate the intended main VCO frequency based on handoff */
 163 static unsigned int cm_calc_handoff_main_vco_clk_hz
 164                                         (struct mainpll_cfg *main_cfg)
 165 {
 166         unsigned int clk_hz;
 167
 168         /* Check main VCO clock source: eosc, intosc or f2s? */
 169         switch (main_cfg->vco0_psrc) {
 170         case CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
 171                 clk_hz = eosc1_hz;
 172                 break;
 173         case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
 174                 clk_hz = cb_intosc_hz;
 175                 break;
 176         case CLKMGR_MAINPLL_VCO0_PSRC_F2S:
 177                 clk_hz = f2s_free_hz;
 178                 break;
 179         default:
 180                 return 0;
 181         }
 182
 183         /* calculate the VCO frequency */
 184         clk_hz /= 1 + main_cfg->vco1_denom;
 185         clk_hz *= 1 + main_cfg->vco1_numer;
 186
 187         return clk_hz;
 188 }
 189
 190 /* calculate the intended periph VCO frequency based on handoff */
 191 static unsigned int cm_calc_handoff_periph_vco_clk_hz(
 192                 struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 193 {
 194         unsigned int clk_hz;
 195
 196         /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */
 197         switch (per_cfg->vco0_psrc) {
 198         case CLKMGR_PERPLL_VCO0_PSRC_EOSC:
 199                 clk_hz = eosc1_hz;
 200                 break;
 201         case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
 202                 clk_hz = cb_intosc_hz;
 203                 break;
 204         case CLKMGR_PERPLL_VCO0_PSRC_F2S:
 205                 clk_hz = f2s_free_hz;
 206                 break;
 207         case CLKMGR_PERPLL_VCO0_PSRC_MAIN:
 208                 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 209                 clk_hz /= main_cfg->cntr15clk_cnt;
 210                 break;
 211         default:
 212                 return 0;
 213         }
 214
 215         /* calculate the VCO frequency */
 216         clk_hz /= 1 + per_cfg->vco1_denom;
 217         clk_hz *= 1 + per_cfg->vco1_numer;
 218
 219         return clk_hz;
 220 }
 221
 222 /* calculate the intended MPU clock frequency based on handoff */
 223 static unsigned int cm_calc_handoff_mpu_clk_hz(struct mainpll_cfg *main_cfg,
 224                                                struct perpll_cfg *per_cfg)
 225 {
 226         unsigned int clk_hz;
 227
 228         /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
 229         switch (main_cfg->mpuclk_src) {
 230         case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN:
 231                 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 232                 clk_hz /= (main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK)
 233                            + 1;
 234                 break;
 235         case CLKMGR_MAINPLL_MPUCLK_SRC_PERI:
 236                 clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
 237                 clk_hz /= ((main_cfg->mpuclk >>
 238                            CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
 239                            CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1;
 240                 break;
 241         case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1:
 242                 clk_hz = eosc1_hz;
 243                 break;
 244         case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC:
 245                 clk_hz = cb_intosc_hz;
 246                 break;
 247         case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA:
 248                 clk_hz = f2s_free_hz;
 249                 break;
 250         default:
 251                 return 0;
 252         }
 253
 254         clk_hz /= main_cfg->mpuclk_cnt + 1;
 255         return clk_hz;
 256 }
 257
 258 /* calculate the intended NOC clock frequency based on handoff */
 259 static unsigned int cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg,
 260                                                struct perpll_cfg *per_cfg)
 261 {
 262         unsigned int clk_hz;
 263
 264         /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
 265         switch (main_cfg->nocclk_src) {
 266         case CLKMGR_MAINPLL_NOCCLK_SRC_MAIN:
 267                 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 268                 clk_hz /= (main_cfg->nocclk & CLKMGR_MAINPLL_NOCCLK_CNT_MSK)
 269                          + 1;
 270                 break;
 271         case CLKMGR_MAINPLL_NOCCLK_SRC_PERI:
 272                 clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
 273                 clk_hz /= ((main_cfg->nocclk >>
 274                            CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
 275                            CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1;
 276                 break;
 277         case CLKMGR_MAINPLL_NOCCLK_SRC_OSC1:
 278                 clk_hz = eosc1_hz;
 279                 break;
 280         case CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC:
 281                 clk_hz = cb_intosc_hz;
 282                 break;
 283         case CLKMGR_MAINPLL_NOCCLK_SRC_FPGA:
 284                 clk_hz = f2s_free_hz;
 285                 break;
 286         default:
 287                 return 0;
 288         }
 289
 290         clk_hz /= main_cfg->nocclk_cnt + 1;
 291         return clk_hz;
 292 }
 293
 294 /* return 1 if PLL ramp is required */
 295 static int cm_is_pll_ramp_required(int main0periph1,
 296                                    struct mainpll_cfg *main_cfg,
 297                                    struct perpll_cfg *per_cfg)
 298 {
 299         /* Check for main PLL */
 300         if (main0periph1 == 0) {
 301                 /*
 302                  * PLL ramp is not required if both MPU clock and NOC clock are
 303                  * not sourced from main PLL
 304                  */
 305                 if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
 306                     main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN)
 307                         return 0;
 308
 309                 /*
 310                  * PLL ramp is required if MPU clock is sourced from main PLL
 311                  * and MPU clock is over 900MHz (as advised by HW team)
 312                  */
 313                 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
 314                     (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
 315                      CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
 316                         return 1;
 317
 318                 /*
 319                  * PLL ramp is required if NOC clock is sourced from main PLL
 320                  * and NOC clock is over 300MHz (as advised by HW team)
 321                  */
 322                 if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN &&
 323                     (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
 324                      CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
 325                         return 2;
 326
 327         } else if (main0periph1 == 1) {
 328                 /*
 329                  * PLL ramp is not required if both MPU clock and NOC clock are
 330                  * not sourced from periph PLL
 331                  */
 332                 if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
 333                     main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI)
 334                         return 0;
 335
 336                 /*
 337                  * PLL ramp is required if MPU clock are source from periph PLL
 338                  * and MPU clock is over 900MHz (as advised by HW team)
 339                  */
 340                 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
 341                     (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
 342                      CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
 343                         return 1;
 344
 345                 /*
 346                  * PLL ramp is required if NOC clock are source from periph PLL
 347                  * and NOC clock is over 300MHz (as advised by HW team)
 348                  */
 349                 if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI &&
 350                     (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
 351                      CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
 352                         return 2;
 353         }
 354
 355         return 0;
 356 }
 357
 358 static u32 cm_calculate_numer(struct mainpll_cfg *main_cfg,
 359                               struct perpll_cfg *per_cfg,
 360                               u32 safe_hz, u32 clk_hz)
 361 {
 362         u32 cnt;
 363         u32 clk;
 364         u32 shift;
 365         u32 mask;
 366         u32 denom;
 367
 368         if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
 369                 cnt = main_cfg->mpuclk_cnt;
 370                 clk = main_cfg->mpuclk;
 371                 shift = 0;
 372                 mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK;
 373                 denom = main_cfg->vco1_denom;
 374         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
 375                 cnt = main_cfg->nocclk_cnt;
 376                 clk = main_cfg->nocclk;
 377                 shift = 0;
 378                 mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK;
 379                 denom = main_cfg->vco1_denom;
 380         } else if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
 381                 cnt = main_cfg->mpuclk_cnt;
 382                 clk = main_cfg->mpuclk;
 383                 shift = CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB;
 384                 mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK;
 385                 denom = per_cfg->vco1_denom;
 386         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
 387                 cnt = main_cfg->nocclk_cnt;
 388                 clk = main_cfg->nocclk;
 389                 shift = CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB;
 390                 mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK;
 391                 denom = per_cfg->vco1_denom;
 392         } else {
 393                 return 0;
 394         }
 395
 396         return (safe_hz / clk_hz) * (cnt + 1) * (((clk >> shift) & mask) + 1) *
 397                 (1 + denom) - 1;
 398 }
 399
 400 /*
 401  * Calculate the new PLL numerator which is based on existing DTS hand off and
 402  * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the
 403  * numerator while maintaining denominator as denominator will influence the
 404  * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final
 405  * value for numerator is minus with 1 to cater our register value
 406  * representation.
 407  */
 408 static unsigned int cm_calc_safe_pll_numer(int main0periph1,
 409                                            struct mainpll_cfg *main_cfg,
 410                                            struct perpll_cfg *per_cfg,
 411                                            unsigned int safe_hz)
 412 {
 413         unsigned int clk_hz = 0;
 414
 415         /* Check for main PLL */
 416         if (main0periph1 == 0) {
 417                 /* Check main VCO clock source: eosc, intosc or f2s? */
 418                 switch (main_cfg->vco0_psrc) {
 419                 case CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
 420                         clk_hz = eosc1_hz;
 421                         break;
 422                 case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
 423                         clk_hz = cb_intosc_hz;
 424                         break;
 425                 case CLKMGR_MAINPLL_VCO0_PSRC_F2S:
 426                         clk_hz = f2s_free_hz;
 427                         break;
 428                 default:
 429                         return 0;
 430                 }
 431         } else if (main0periph1 == 1) {
 432                 /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */
 433                 switch (per_cfg->vco0_psrc) {
 434                 case CLKMGR_PERPLL_VCO0_PSRC_EOSC:
 435                         clk_hz = eosc1_hz;
 436                         break;
 437                 case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
 438                         clk_hz = cb_intosc_hz;
 439                         break;
 440                 case CLKMGR_PERPLL_VCO0_PSRC_F2S:
 441                         clk_hz = f2s_free_hz;
 442                         break;
 443                 case CLKMGR_PERPLL_VCO0_PSRC_MAIN:
 444                         clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 445                         clk_hz /= main_cfg->cntr15clk_cnt;
 446                         break;
 447                 default:
 448                         return 0;
 449                 }
 450         } else {
 451                 return 0;
 452         }
 453
 454         return cm_calculate_numer(main_cfg, per_cfg, safe_hz, clk_hz);
 455 }
 456
 457 /* ramping the main PLL to final value */
 458 static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
 459                              struct perpll_cfg *per_cfg,
 460                              unsigned int pll_ramp_main_hz)
 461 {
 462         unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0;
 463
 464         /* find out the increment value */
 465         if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
 466                 clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
 467                 clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
 468         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
 469                 clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
 470                 clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
 471         }
 472
 473         /* execute the ramping here */
 474         for (clk_hz = pll_ramp_main_hz + clk_incr_hz;
 475              clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
 476                 writel((main_cfg->vco1_denom <<
 477                         CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 478                         cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
 479                         &clock_manager_base->main_pll.vco1);
 480                 mdelay(1);
 481                 cm_wait_for_lock(LOCKED_MASK);
 482         }
 483         writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 484                 main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1);
 485         mdelay(1);
 486         cm_wait_for_lock(LOCKED_MASK);
 487 }
 488
 489 /* ramping the periph PLL to final value */
 490 static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg,
 491                                struct perpll_cfg *per_cfg,
 492                                unsigned int pll_ramp_periph_hz)
 493 {
 494         unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0;
 495
 496         /* find out the increment value */
 497         if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
 498                 clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
 499                 clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
 500         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
 501                 clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
 502                 clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
 503         }
 504         /* execute the ramping here */
 505         for (clk_hz = pll_ramp_periph_hz + clk_incr_hz;
 506              clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
 507                 writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 508                         cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz),
 509                         &clock_manager_base->per_pll.vco1);
 510                 mdelay(1);
 511                 cm_wait_for_lock(LOCKED_MASK);
 512         }
 513         writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 514                 per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1);
 515         mdelay(1);
 516         cm_wait_for_lock(LOCKED_MASK);
 517 }
 518
 519 /*
 520  * Setup clocks while making no assumptions of the
 521  * previous state of the clocks.
 522  *
 523  * Start by being paranoid and gate all sw managed clocks
 524  *
 525  * Put all plls in bypass
 526  *
 527  * Put all plls VCO registers back to reset value (bgpwr dwn).
 528  *
 529  * Put peripheral and main pll src to reset value to avoid glitch.
 530  *
 531  * Delay 5 us.
 532  *
 533  * Deassert bg pwr dn and set numerator and denominator
 534  *
 535  * Start 7 us timer.
 536  *
 537  * set internal dividers
 538  *
 539  * Wait for 7 us timer.
 540  *
 541  * Enable plls
 542  *
 543  * Set external dividers while plls are locking
 544  *
 545  * Wait for pll lock
 546  *
 547  * Assert/deassert outreset all.
 548  *
 549  * Take all pll's out of bypass
 550  *
 551  * Clear safe mode
 552  *
 553  * set source main and peripheral clocks
 554  *
 555  * Ungate clocks
 556  */
 557
 558 static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 559 {
 560         unsigned int pll_ramp_main_hz = 0, pll_ramp_periph_hz = 0,
 561                 ramp_required;
 562
 563         /* gate off all mainpll clock excpet HW managed clock */
 564         writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
 565                 CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
 566                 &clock_manager_base->main_pll.enr);
 567
 568         /* now we can gate off the rest of the peripheral clocks */
 569         writel(0, &clock_manager_base->per_pll.en);
 570
 571         /* Put all plls in external bypass */
 572         writel(CLKMGR_MAINPLL_BYPASS_RESET,
 573                &clock_manager_base->main_pll.bypasss);
 574         writel(CLKMGR_PERPLL_BYPASS_RESET,
 575                &clock_manager_base->per_pll.bypasss);
 576
 577         /*
 578          * Put all plls VCO registers back to reset value.
 579          * Some code might have messed with them. At same time set the
 580          * desired clock source
 581          */
 582         writel(CLKMGR_MAINPLL_VCO0_RESET |
 583                CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK |
 584                (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB),
 585                &clock_manager_base->main_pll.vco0);
 586
 587         writel(CLKMGR_PERPLL_VCO0_RESET |
 588                CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK |
 589                (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB),
 590                &clock_manager_base->per_pll.vco0);
 591
 592         writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1);
 593         writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1);
 594
 595         /* clear the interrupt register status register */
 596         writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
 597                 CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
 598                 CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
 599                 CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
 600                 CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
 601                 CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK |
 602                 CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK |
 603                 CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK,
 604                 &clock_manager_base->intr);
 605
 606         /* Program VCO Numerator and Denominator for main PLL */
 607         ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg);
 608         if (ramp_required) {
 609                 /* set main PLL to safe starting threshold frequency */
 610                 if (ramp_required == 1)
 611                         pll_ramp_main_hz = CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
 612                 else if (ramp_required == 2)
 613                         pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
 614
 615                 writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 616                         cm_calc_safe_pll_numer(0, main_cfg, per_cfg,
 617                                                pll_ramp_main_hz),
 618                         &clock_manager_base->main_pll.vco1);
 619         } else
 620                 writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 621                         main_cfg->vco1_numer,
 622                         &clock_manager_base->main_pll.vco1);
 623
 624         /* Program VCO Numerator and Denominator for periph PLL */
 625         ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg);
 626         if (ramp_required) {
 627                 /* set periph PLL to safe starting threshold frequency */
 628                 if (ramp_required == 1)
 629                         pll_ramp_periph_hz =
 630                                 CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
 631                 else if (ramp_required == 2)
 632                         pll_ramp_periph_hz =
 633                                 CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
 634
 635                 writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 636                         cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
 637                                                pll_ramp_periph_hz),
 638                         &clock_manager_base->per_pll.vco1);
 639         } else
 640                 writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 641                         per_cfg->vco1_numer,
 642                         &clock_manager_base->per_pll.vco1);
 643
 644         /* Wait for at least 5 us */
 645         udelay(5);
 646
 647         /* Now deassert BGPWRDN and PWRDN */
 648         clrbits_le32(&clock_manager_base->main_pll.vco0,
 649                      CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK |
 650                      CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK);
 651         clrbits_le32(&clock_manager_base->per_pll.vco0,
 652                      CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK |
 653                      CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
 654
 655         /* Wait for at least 7 us */
 656         udelay(7);
 657
 658         /* enable the VCO and disable the external regulator to PLL */
 659         writel((readl(&clock_manager_base->main_pll.vco0) &
 660                 ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) |
 661                 CLKMGR_MAINPLL_VCO0_EN_SET_MSK,
 662                 &clock_manager_base->main_pll.vco0);
 663         writel((readl(&clock_manager_base->per_pll.vco0) &
 664                 ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) |
 665                 CLKMGR_PERPLL_VCO0_EN_SET_MSK,
 666                 &clock_manager_base->per_pll.vco0);
 667
 668         /* setup all the main PLL counter and clock source */
 669         writel(main_cfg->nocclk,
 670                SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET);
 671         writel(main_cfg->mpuclk,
 672                SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET);
 673
 674         /* main_emaca_clk divider */
 675         writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk);
 676         /* main_emacb_clk divider */
 677         writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk);
 678         /* main_emac_ptp_clk divider */
 679         writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk);
 680         /* main_gpio_db_clk divider */
 681         writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk);
 682         /* main_sdmmc_clk divider */
 683         writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk);
 684         /* main_s2f_user0_clk divider */
 685         writel(main_cfg->cntr7clk_cnt |
 686                (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB),
 687                &clock_manager_base->main_pll.cntr7clk);
 688         /* main_s2f_user1_clk divider */
 689         writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk);
 690         /* main_hmc_pll_clk divider */
 691         writel(main_cfg->cntr9clk_cnt |
 692                (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB),
 693                &clock_manager_base->main_pll.cntr9clk);
 694         /* main_periph_ref_clk divider */
 695         writel(main_cfg->cntr15clk_cnt,
 696                &clock_manager_base->main_pll.cntr15clk);
 697
 698         /* setup all the peripheral PLL counter and clock source */
 699         /* peri_emaca_clk divider */
 700         writel(per_cfg->cntr2clk_cnt |
 701                (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB),
 702                &clock_manager_base->per_pll.cntr2clk);
 703         /* peri_emacb_clk divider */
 704         writel(per_cfg->cntr3clk_cnt |
 705                (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB),
 706                &clock_manager_base->per_pll.cntr3clk);
 707         /* peri_emac_ptp_clk divider */
 708         writel(per_cfg->cntr4clk_cnt |
 709                (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB),
 710                &clock_manager_base->per_pll.cntr4clk);
 711         /* peri_gpio_db_clk divider */
 712         writel(per_cfg->cntr5clk_cnt |
 713                (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB),
 714                &clock_manager_base->per_pll.cntr5clk);
 715         /* peri_sdmmc_clk divider */
 716         writel(per_cfg->cntr6clk_cnt |
 717                (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB),
 718                &clock_manager_base->per_pll.cntr6clk);
 719         /* peri_s2f_user0_clk divider */
 720         writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk);
 721         /* peri_s2f_user1_clk divider */
 722         writel(per_cfg->cntr8clk_cnt |
 723                (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB),
 724                &clock_manager_base->per_pll.cntr8clk);
 725         /* peri_hmc_pll_clk divider */
 726         writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk);
 727
 728         /* setup all the external PLL counter */
 729         /* mpu wrapper / external divider */
 730         writel(main_cfg->mpuclk_cnt |
 731                (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB),
 732                &clock_manager_base->main_pll.mpuclk);
 733         /* NOC wrapper / external divider */
 734         writel(main_cfg->nocclk_cnt |
 735                (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB),
 736                &clock_manager_base->main_pll.nocclk);
 737         /* NOC subclock divider such as l4 */
 738         writel(main_cfg->nocdiv_l4mainclk |
 739                (main_cfg->nocdiv_l4mpclk <<
 740                 CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) |
 741                (main_cfg->nocdiv_l4spclk <<
 742                 CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) |
 743                (main_cfg->nocdiv_csatclk <<
 744                 CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) |
 745                (main_cfg->nocdiv_cstraceclk <<
 746                 CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) |
 747                (main_cfg->nocdiv_cspdbclk <<
 748                 CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB),
 749                 &clock_manager_base->main_pll.nocdiv);
 750         /* gpio_db external divider */
 751         writel(per_cfg->gpiodiv_gpiodbclk,
 752                &clock_manager_base->per_pll.gpiodiv);
 753
 754         /* setup the EMAC clock mux select */
 755         writel((per_cfg->emacctl_emac0sel <<
 756                 CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) |
 757                (per_cfg->emacctl_emac1sel <<
 758                 CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) |
 759                (per_cfg->emacctl_emac2sel <<
 760                 CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB),
 761                &clock_manager_base->per_pll.emacctl);
 762
 763         /* at this stage, check for PLL lock status */
 764         cm_wait_for_lock(LOCKED_MASK);
 765
 766         /*
 767          * after locking, but before taking out of bypass,
 768          * assert/deassert outresetall
 769          */
 770         /* assert mainpll outresetall */
 771         setbits_le32(&clock_manager_base->main_pll.vco0,
 772                      CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
 773         /* assert perpll outresetall */
 774         setbits_le32(&clock_manager_base->per_pll.vco0,
 775                      CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
 776         /* de-assert mainpll outresetall */
 777         clrbits_le32(&clock_manager_base->main_pll.vco0,
 778                      CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
 779         /* de-assert perpll outresetall */
 780         clrbits_le32(&clock_manager_base->per_pll.vco0,
 781                      CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
 782
 783         /* Take all PLLs out of bypass when boot mode is cleared. */
 784         /* release mainpll from bypass */
 785         writel(CLKMGR_MAINPLL_BYPASS_RESET,
 786                &clock_manager_base->main_pll.bypassr);
 787         /* wait till Clock Manager is not busy */
 788         cm_wait_for_fsm();
 789
 790         /* release perpll from bypass */
 791         writel(CLKMGR_PERPLL_BYPASS_RESET,
 792                &clock_manager_base->per_pll.bypassr);
 793         /* wait till Clock Manager is not busy */
 794         cm_wait_for_fsm();
 795
 796         /* clear boot mode */
 797         clrbits_le32(&clock_manager_base->ctrl,
 798                      CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
 799         /* wait till Clock Manager is not busy */
 800         cm_wait_for_fsm();
 801
 802         /* At here, we need to ramp to final value if needed */
 803         if (pll_ramp_main_hz != 0)
 804                 cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz);
 805         if (pll_ramp_periph_hz != 0)
 806                 cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz);
 807
 808         /* Now ungate non-hw-managed clocks */
 809         writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
 810                 CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
 811                 &clock_manager_base->main_pll.ens);
 812         writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens);
 813
 814         /* Clear the loss lock and slip bits as they might set during
 815         clock reconfiguration */
 816         writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
 817                CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
 818                CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
 819                CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
 820                CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
 821                CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK,
 822                &clock_manager_base->intr);
 823
 824         return 0;
 825 }
 826
 827 void cm_use_intosc(void)
 828 {
 829         setbits_le32(&clock_manager_base->ctrl,
 830                      CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK);
 831 }
 832
 833 unsigned int cm_get_noc_clk_hz(void)
 834 {
 835         unsigned int clk_src, divisor, nocclk, src_hz;
 836
 837         nocclk = readl(&clock_manager_base->main_pll.nocclk);
 838         clk_src = (nocclk >> CLKMGR_MAINPLL_NOCCLK_SRC_LSB) &
 839                   CLKMGR_MAINPLL_NOCCLK_SRC_MSK;
 840
 841         divisor = 1 + (nocclk & CLKMGR_MAINPLL_NOCDIV_MSK);
 842
 843         if (clk_src == CLKMGR_PERPLLGRP_SRC_MAIN) {
 844                 src_hz = cm_get_main_vco_clk_hz();
 845                 src_hz /= 1 +
 846                 (readl(SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET) &
 847                 CLKMGR_MAINPLL_NOCCLK_CNT_MSK);
 848         } else if (clk_src == CLKMGR_PERPLLGRP_SRC_PERI) {
 849                 src_hz = cm_get_per_vco_clk_hz();
 850                 src_hz /= 1 +
 851                 ((readl(SOCFPGA_CLKMGR_ADDRESS +
 852                         CLKMGR_MAINPLL_NOC_CLK_OFFSET) >>
 853                         CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
 854                         CLKMGR_MAINPLL_NOCCLK_CNT_MSK);
 855         } else if (clk_src == CLKMGR_PERPLLGRP_SRC_OSC1) {
 856                 src_hz = eosc1_hz;
 857         } else if (clk_src == CLKMGR_PERPLLGRP_SRC_INTOSC) {
 858                 src_hz = cb_intosc_hz;
 859         } else if (clk_src == CLKMGR_PERPLLGRP_SRC_FPGA) {
 860                 src_hz = f2s_free_hz;
 861         } else {
 862                 src_hz = 0;
 863         }
 864
 865         return src_hz / divisor;
 866 }
 867
 868 unsigned int cm_get_l4_noc_hz(unsigned int nocdivshift)
 869 {
 870         unsigned int divisor2 = 1 <<
 871                 ((readl(&clock_manager_base->main_pll.nocdiv) >>
 872                         nocdivshift) & CLKMGR_MAINPLL_NOCDIV_MSK);
 873
 874         return cm_get_noc_clk_hz() / divisor2;
 875 }
 876
 877 int cm_basic_init(const void *blob)
 878 {
 879         struct mainpll_cfg main_cfg;
 880         struct perpll_cfg per_cfg;
 881         struct alteragrp_cfg altrgrp_cfg;
 882         int rval;
 883
 884         /* initialize to zero for use case of optional node */
 885         memset(&main_cfg, 0, sizeof(main_cfg));
 886         memset(&per_cfg, 0, sizeof(per_cfg));
 887         memset(&altrgrp_cfg, 0, sizeof(altrgrp_cfg));
 888
 889         rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg, &altrgrp_cfg);
 890         if (rval)
 891                 return rval;
 892
 893         rval =  cm_full_cfg(&main_cfg, &per_cfg);
 894
 895         cm_l4_main_clk_hz =
 896                 cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB);
 897
 898         cm_l4_mp_clk_hz = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
 899
 900         cm_l4_sp_clk_hz = cm_get_l4_sp_clk_hz();
 901
 902         cm_l4_sys_free_clk_hz = cm_get_noc_clk_hz() / 4;
 903
 904         return rval;
 905 }
 906
 907 unsigned long cm_get_mpu_clk_hz(void)
 908 {
 909         u32 reg, clk_hz;
 910         u32 clk_src, mainmpuclk_reg;
 911
 912         mainmpuclk_reg = readl(&clock_manager_base->main_pll.mpuclk);
 913
 914         clk_src = (mainmpuclk_reg >> CLKMGR_MAINPLL_MPUCLK_SRC_LSB) &
 915                 CLKMGR_MAINPLL_MPUCLK_SRC_MSK;
 916
 917         reg = readl(&clock_manager_base->altera.mpuclk);
 918         /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
 919         switch (clk_src) {
 920         case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN:
 921                 clk_hz = cm_get_main_vco_clk_hz();
 922                 clk_hz /= (reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1;
 923                 break;
 924         case CLKMGR_MAINPLL_MPUCLK_SRC_PERI:
 925                 clk_hz = cm_get_per_vco_clk_hz();
 926                 clk_hz /= (((reg >> CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
 927                            CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1);
 928                 break;
 929         case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1:
 930                 clk_hz = eosc1_hz;
 931                 break;
 932         case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC:
 933                 clk_hz = cb_intosc_hz;
 934                 break;
 935         case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA:
 936                 clk_hz = f2s_free_hz;
 937                 break;
 938         default:
 939                 printf("cm_get_mpu_clk_hz invalid clk_src %d\n", clk_src);
 940                 return 0;
 941         }
 942
 943         clk_hz /= (mainmpuclk_reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1;
 944
 945         return clk_hz;
 946 }
 947
 948 unsigned int cm_get_per_vco_clk_hz(void)
 949 {
 950         u32 src_hz = 0;
 951         u32 clk_src = 0;
 952         u32 numer = 0;
 953         u32 denom = 0;
 954         u32 vco = 0;
 955
 956         clk_src = readl(&clock_manager_base->per_pll.vco0);
 957
 958         clk_src = (clk_src >> CLKMGR_PERPLL_VCO0_PSRC_LSB) &
 959                 CLKMGR_PERPLL_VCO0_PSRC_MSK;
 960
 961         if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_EOSC) {
 962                 src_hz = eosc1_hz;
 963         } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC) {
 964                 src_hz = cb_intosc_hz;
 965         } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_F2S) {
 966                 src_hz = f2s_free_hz;
 967         } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_MAIN) {
 968                 src_hz = cm_get_main_vco_clk_hz();
 969                 src_hz /= (readl(&clock_manager_base->main_pll.cntr15clk) &
 970                         CLKMGR_MAINPLL_CNTRCLK_MSK) + 1;
 971         } else {
 972                 printf("cm_get_per_vco_clk_hz invalid clk_src %d\n", clk_src);
 973                 return 0;
 974         }
 975
 976         vco = readl(&clock_manager_base->per_pll.vco1);
 977
 978         numer = vco & CLKMGR_PERPLL_VCO1_NUMER_MSK;
 979
 980         denom = (vco >> CLKMGR_PERPLL_VCO1_DENOM_LSB) &
 981                         CLKMGR_PERPLL_VCO1_DENOM_MSK;
 982
 983         vco = src_hz;
 984         vco /= 1 + denom;
 985         vco *= 1 + numer;
 986
 987         return vco;
 988 }
 989
 990 unsigned int cm_get_main_vco_clk_hz(void)
 991 {
 992         u32 src_hz, numer, denom, vco;
 993
 994         u32 clk_src = readl(&clock_manager_base->main_pll.vco0);
 995
 996         clk_src = (clk_src >> CLKMGR_MAINPLL_VCO0_PSRC_LSB) &
 997                 CLKMGR_MAINPLL_VCO0_PSRC_MSK;
 998
 999         if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_EOSC) {
1000                 src_hz = eosc1_hz;
1001         } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC) {
1002                 src_hz = cb_intosc_hz;
1003         } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_F2S) {
1004                 src_hz = f2s_free_hz;
1005         } else {
1006                 printf("cm_get_main_vco_clk_hz invalid clk_src %d\n", clk_src);
1007                 return 0;
1008         }
1009
1010         vco = readl(&clock_manager_base->main_pll.vco1);
1011
1012         numer = vco & CLKMGR_MAINPLL_VCO1_NUMER_MSK;
1013
1014         denom = (vco >> CLKMGR_MAINPLL_VCO1_DENOM_LSB) &
1015                         CLKMGR_MAINPLL_VCO1_DENOM_MSK;
1016
1017         vco = src_hz;
1018         vco /= 1 + denom;
1019         vco *= 1 + numer;
1020
1021         return vco;
1022 }
1023
1024 unsigned int cm_get_l4_sp_clk_hz(void)
1025 {
1026         return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB);
1027 }
1028
1029 unsigned int cm_get_mmc_controller_clk_hz(void)
1030 {
1031         u32 clk_hz = 0;
1032         u32 clk_input = 0;
1033
1034         clk_input = readl(&clock_manager_base->per_pll.cntr6clk);
1035         clk_input = (clk_input >> CLKMGR_PERPLL_CNTR6CLK_SRC_LSB) &
1036                 CLKMGR_PERPLLGRP_SRC_MSK;
1037
1038         switch (clk_input) {
1039         case CLKMGR_PERPLLGRP_SRC_MAIN:
1040                 clk_hz = cm_get_main_vco_clk_hz();
1041                 clk_hz /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &
1042                         CLKMGR_MAINPLL_CNTRCLK_MSK);
1043                 break;
1044
1045         case CLKMGR_PERPLLGRP_SRC_PERI:
1046                 clk_hz = cm_get_per_vco_clk_hz();
1047                 clk_hz /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &
1048                         CLKMGR_PERPLL_CNTRCLK_MSK);
1049                 break;
1050
1051         case CLKMGR_PERPLLGRP_SRC_OSC1:
1052                 clk_hz = eosc1_hz;
1053                 break;
1054
1055         case CLKMGR_PERPLLGRP_SRC_INTOSC:
1056                 clk_hz = cb_intosc_hz;
1057                 break;
1058
1059         case CLKMGR_PERPLLGRP_SRC_FPGA:
1060                 clk_hz = f2s_free_hz;
1061                 break;
1062         }
1063
1064         return clk_hz / 4;
1065 }
1066
1067 unsigned int cm_get_spi_controller_clk_hz(void)
1068 {
1069         return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
1070 }
1071
1072 unsigned int cm_get_qspi_controller_clk_hz(void)
1073 {
1074         return  cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB);
1075 }
1076
1077 /* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
1078 int dw_spi_get_clk(struct udevice *bus, ulong *rate)
1079 {
1080         *rate = cm_get_spi_controller_clk_hz();
1081
1082         return 0;
1083 }
1084
1085 void cm_print_clock_quick_summary(void)
1086 {
1087         printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
1088         printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
1089         printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
1090         printf("SPI         %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
1091         printf("EOSC1       %8d kHz\n", eosc1_hz / 1000);
1092         printf("cb_intosc   %8d kHz\n", cb_intosc_hz / 1000);
1093         printf("f2s_free    %8d kHz\n", f2s_free_hz / 1000);
1094         printf("Main VCO    %8d kHz\n", cm_get_main_vco_clk_hz() / 1000);
1095         printf("NOC         %8d kHz\n", cm_get_noc_clk_hz() / 1000);
1096         printf("L4 Main     %8d kHz\n",
1097                cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB) / 1000);
1098         printf("L4 MP       %8d kHz\n",
1099                cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) / 1000);
1100         printf("L4 SP       %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
1101         printf("L4 sys free %8d kHz\n", cm_l4_sys_free_clk_hz / 1000);
1102 }