1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
9 #include <asm/arch/clock_manager.h>
11 DECLARE_GLOBAL_DATA_PTR;
13 static const struct socfpga_clock_manager *clock_manager_base =
14 (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
16 void cm_wait_for_lock(u32 mask)
21 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
22 inter_val = readl(&clock_manager_base->inter) & mask;
24 inter_val = readl(&clock_manager_base->stat) & mask;
26 /* Wait for stable lock */
27 if (inter_val == mask)
36 /* function to poll in the fsm busy bit */
37 int cm_wait_for_fsm(void)
39 return wait_for_bit_le32(&clock_manager_base->stat,
40 CLKMGR_STAT_BUSY, false, 20000, false);
43 int set_cpu_clk_info(void)
45 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
46 /* Calculate the clock frequencies required for drivers */
47 cm_get_l4_sp_clk_hz();
48 cm_get_mmc_controller_clk_hz();
51 gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
52 gd->bd->bi_dsp_freq = 0;
54 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
55 gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
57 gd->bd->bi_ddr_freq = 0;
63 #ifndef CONFIG_SPL_BUILD
64 static int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
66 cm_print_clock_quick_summary();
71 clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,