1 // SPDX-License-Identifier: GPL-2.0+
3 * Altera SoCFPGA common board code
5 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
12 #include <asm/arch/reset_manager.h>
13 #include <asm/arch/clock_manager.h>
14 #include <asm/arch/misc.h>
18 #include <usb/dwc2_udc.h>
20 DECLARE_GLOBAL_DATA_PTR;
25 * Preconfigure ACTLR and CPACR, make sure Write Full Line of Zeroes
26 * is disabled in ACTLR.
27 * This is optional on CycloneV / ArriaV.
28 * This is mandatory on Arria10, otherwise Linux refuses to boot.
31 "mcr p15, 0, %0, c1, c0, 1\n"
32 "mcr p15, 0, %0, c1, c0, 2\n"
40 * Miscellaneous platform dependent initialisations
44 /* Address of boot parameters for ATAG (if ATAG is used) */
45 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
50 int dram_init_banksize(void)
52 fdtdec_setup_memory_banksize();
57 #ifdef CONFIG_USB_GADGET
58 struct dwc2_plat_otg_data socfpga_otg_data = {
59 .usb_gusbcfg = 0x1417,
62 int board_usb_init(int index, enum usb_init_type init)
67 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
68 COMPAT_ALTERA_SOCFPGA_DWC2USB,
70 if (count <= 0) /* No controller found. */
73 addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
74 if (addr == FDT_ADDR_T_NONE) {
75 printf("UDC Controller has no 'reg' property!\n");
79 /* Patch the address from OF into the controller pdata. */
80 socfpga_otg_data.regs_otg = addr;
82 return dwc2_udc_probe(&socfpga_otg_data);
85 int g_dnl_board_usb_cable_connected(void)