1 // SPDX-License-Identifier: GPL-2.0+
3 * Altera SoCFPGA common board code
5 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
11 #include <asm/arch/reset_manager.h>
12 #include <asm/arch/clock_manager.h>
13 #include <asm/arch/misc.h>
17 #include <usb/dwc2_udc.h>
19 DECLARE_GLOBAL_DATA_PTR;
24 * Preconfigure ACTLR, make sure Write Full Line of Zeroes is disabled.
25 * This is optional on CycloneV / ArriaV.
26 * This is mandatory on Arria10, otherwise Linux refuses to boot.
29 "mcr p15, 0, %0, c1, c0, 1\n"
37 * Miscellaneous platform dependent initialisations
41 /* Address of boot parameters for ATAG (if ATAG is used) */
42 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
44 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
45 /* configuring the clock based on handoff */
46 cm_basic_init(gd->fdt_blob);
48 /* Add device descriptor to FPGA device table */
55 int dram_init_banksize(void)
57 fdtdec_setup_memory_banksize();
62 #ifdef CONFIG_USB_GADGET
63 struct dwc2_plat_otg_data socfpga_otg_data = {
64 .usb_gusbcfg = 0x1417,
67 int board_usb_init(int index, enum usb_init_type init)
72 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
73 COMPAT_ALTERA_SOCFPGA_DWC2USB,
75 if (count <= 0) /* No controller found. */
78 addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
79 if (addr == FDT_ADDR_T_NONE) {
80 printf("UDC Controller has no 'reg' property!\n");
84 /* Patch the address from OF into the controller pdata. */
85 socfpga_otg_data.regs_otg = addr;
87 return dwc2_udc_probe(&socfpga_otg_data);
90 int g_dnl_board_usb_cable_connected(void)