6 config SPL_STACK_R_ADDR
7 default 0x00800000 if TARGET_SOCFPGA_GEN5
9 config SPL_SYS_MALLOC_F_LEN
10 default 0x800 if TARGET_SOCFPGA_GEN5
12 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
15 config SYS_MALLOC_F_LEN
16 default 0x2000 if TARGET_SOCFPGA_ARRIA10
17 default 0x2000 if TARGET_SOCFPGA_GEN5
20 default 0x01000040 if TARGET_SOCFPGA_ARRIA10
21 default 0x01000040 if TARGET_SOCFPGA_GEN5
23 config TARGET_SOCFPGA_ARRIA5
25 select TARGET_SOCFPGA_GEN5
27 config TARGET_SOCFPGA_ARRIA10
30 select SPL_BOARD_INIT if SPL
35 select SPL_DM_RESET if SPL
37 select SPL_REGMAP if SPL
39 select SPL_SYSCON if SPL
40 select ETH_DESIGNWARE_SOCFPGA
44 config TARGET_SOCFPGA_CYCLONE5
46 select TARGET_SOCFPGA_GEN5
48 config TARGET_SOCFPGA_GEN5
53 imply SPL_SYS_MALLOC_SIMPLE
56 config TARGET_SOCFPGA_STRATIX10
58 select ARMV8_MULTIENTRY
59 select ARMV8_SET_SMPEN
60 select ARMV8_SPIN_TABLE
64 prompt "Altera SOCFPGA board select"
67 config TARGET_SOCFPGA_ARRIA10_SOCDK
68 bool "Altera SOCFPGA SoCDK (Arria 10)"
69 select TARGET_SOCFPGA_ARRIA10
71 config TARGET_SOCFPGA_ARRIA5_SOCDK
72 bool "Altera SOCFPGA SoCDK (Arria V)"
73 select TARGET_SOCFPGA_ARRIA5
75 config TARGET_SOCFPGA_CYCLONE5_SOCDK
76 bool "Altera SOCFPGA SoCDK (Cyclone V)"
77 select TARGET_SOCFPGA_CYCLONE5
79 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
80 bool "Devboards DBM-SoC1 (Cyclone V)"
81 select TARGET_SOCFPGA_CYCLONE5
83 config TARGET_SOCFPGA_EBV_SOCRATES
84 bool "EBV SoCrates (Cyclone V)"
85 select TARGET_SOCFPGA_CYCLONE5
87 config TARGET_SOCFPGA_IS1
88 bool "IS1 (Cyclone V)"
89 select TARGET_SOCFPGA_CYCLONE5
91 config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
92 bool "samtec VIN|ING FPGA (Cyclone V)"
93 select BOARD_LATE_INIT
94 select TARGET_SOCFPGA_CYCLONE5
96 config TARGET_SOCFPGA_SR1500
97 bool "SR1500 (Cyclone V)"
98 select TARGET_SOCFPGA_CYCLONE5
100 config TARGET_SOCFPGA_STRATIX10_SOCDK
101 bool "Intel SOCFPGA SoCDK (Stratix 10)"
102 select TARGET_SOCFPGA_STRATIX10
104 config TARGET_SOCFPGA_TERASIC_DE0_NANO
105 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
106 select TARGET_SOCFPGA_CYCLONE5
108 config TARGET_SOCFPGA_TERASIC_DE10_NANO
109 bool "Terasic DE10-Nano (Cyclone V)"
110 select TARGET_SOCFPGA_CYCLONE5
112 config TARGET_SOCFPGA_TERASIC_DE1_SOC
113 bool "Terasic DE1-SoC (Cyclone V)"
114 select TARGET_SOCFPGA_CYCLONE5
116 config TARGET_SOCFPGA_TERASIC_SOCKIT
117 bool "Terasic SoCkit (Cyclone V)"
118 select TARGET_SOCFPGA_CYCLONE5
123 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
124 default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
125 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
126 default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
127 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
128 default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
129 default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
130 default "is1" if TARGET_SOCFPGA_IS1
131 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
132 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
133 default "sr1500" if TARGET_SOCFPGA_SR1500
134 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
135 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
138 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
139 default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
140 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
141 default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
142 default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
143 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
144 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
145 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
146 default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
147 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
148 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
153 config SYS_CONFIG_NAME
154 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
155 default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
156 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
157 default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
158 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
159 default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
160 default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
161 default "socfpga_is1" if TARGET_SOCFPGA_IS1
162 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
163 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
164 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
165 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
166 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA