arch/arm/mach-socfpga/Kconfig

   1 if ARCH_SOCFPGA
   2
   3 config ERR_PTR_OFFSET
   4         default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
   5
   6 config NR_DRAM_BANKS
   7         default 1
   8
   9 config SPL_SIZE_LIMIT
  10         default 0x10000 if TARGET_SOCFPGA_GEN5
  11
  12 config SPL_SIZE_LIMIT_PROVIDE_STACK
  13         default 0x200 if TARGET_SOCFPGA_GEN5
  14
  15 config SPL_STACK_R_ADDR
  16         default 0x00800000 if TARGET_SOCFPGA_GEN5
  17
  18 config SPL_SYS_MALLOC_F_LEN
  19         default 0x800 if TARGET_SOCFPGA_GEN5
  20
  21 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
  22         default 0xa2
  23
  24 config SYS_MALLOC_F_LEN
  25         default 0x2000 if TARGET_SOCFPGA_ARRIA10
  26         default 0x2000 if TARGET_SOCFPGA_GEN5
  27
  28 config SYS_TEXT_BASE
  29         default 0x01000040 if TARGET_SOCFPGA_ARRIA10
  30         default 0x01000040 if TARGET_SOCFPGA_GEN5
  31
  32 config TARGET_SOCFPGA_AGILEX
  33         bool
  34         select ARMV8_MULTIENTRY
  35         select ARMV8_SET_SMPEN
  36         select ARMV8_SPIN_TABLE
  37         select CLK
  38         select NCORE_CACHE
  39         select SPL_CLK if SPL
  40
  41 config TARGET_SOCFPGA_ARRIA5
  42         bool
  43         select TARGET_SOCFPGA_GEN5
  44
  45 config TARGET_SOCFPGA_ARRIA10
  46         bool
  47         select SPL_ALTERA_SDRAM
  48         select SPL_BOARD_INIT if SPL
  49         select SPL_CACHE if SPL
  50         select CLK
  51         select SPL_CLK if SPL
  52         select DM_I2C
  53         select DM_RESET
  54         select SPL_DM_RESET if SPL
  55         select REGMAP
  56         select SPL_REGMAP if SPL
  57         select SYSCON
  58         select SPL_SYSCON if SPL
  59         select ETH_DESIGNWARE_SOCFPGA
  60         imply FPGA_SOCFPGA
  61         imply SPL_USE_TINY_PRINTF
  62
  63 config TARGET_SOCFPGA_CYCLONE5
  64         bool
  65         select TARGET_SOCFPGA_GEN5
  66
  67 config TARGET_SOCFPGA_GEN5
  68         bool
  69         select SPL_ALTERA_SDRAM
  70         imply FPGA_SOCFPGA
  71         imply SPL_SIZE_LIMIT_SUBTRACT_GD
  72         imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
  73         imply SPL_STACK_R
  74         imply SPL_SYS_MALLOC_SIMPLE
  75         imply SPL_USE_TINY_PRINTF
  76
  77 config TARGET_SOCFPGA_STRATIX10
  78         bool
  79         select ARMV8_MULTIENTRY
  80         select ARMV8_SET_SMPEN
  81         select ARMV8_SPIN_TABLE
  82         select FPGA_STRATIX10
  83
  84 choice
  85         prompt "Altera SOCFPGA board select"
  86         optional
  87
  88 config TARGET_SOCFPGA_AGILEX_SOCDK
  89         bool "Intel SOCFPGA SoCDK (Agilex)"
  90         select TARGET_SOCFPGA_AGILEX
  91
  92 config TARGET_SOCFPGA_ARIES_MCVEVK
  93         bool "Aries MCVEVK (Cyclone V)"
  94         select TARGET_SOCFPGA_CYCLONE5
  95
  96 config TARGET_SOCFPGA_ARRIA10_SOCDK
  97         bool "Altera SOCFPGA SoCDK (Arria 10)"
  98         select TARGET_SOCFPGA_ARRIA10
  99
 100 config TARGET_SOCFPGA_ARRIA5_SECU1
 101         bool "ABB SECU1 (Arria V)"
 102         select TARGET_SOCFPGA_ARRIA5
 103         select VENDOR_KM
 104
 105 config TARGET_SOCFPGA_ARRIA5_SOCDK
 106         bool "Altera SOCFPGA SoCDK (Arria V)"
 107         select TARGET_SOCFPGA_ARRIA5
 108
 109 config TARGET_SOCFPGA_CYCLONE5_SOCDK
 110         bool "Altera SOCFPGA SoCDK (Cyclone V)"
 111         select TARGET_SOCFPGA_CYCLONE5
 112
 113 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 114         bool "Devboards DBM-SoC1 (Cyclone V)"
 115         select TARGET_SOCFPGA_CYCLONE5
 116
 117 config TARGET_SOCFPGA_EBV_SOCRATES
 118         bool "EBV SoCrates (Cyclone V)"
 119         select TARGET_SOCFPGA_CYCLONE5
 120
 121 config TARGET_SOCFPGA_IS1
 122         bool "IS1 (Cyclone V)"
 123         select TARGET_SOCFPGA_CYCLONE5
 124
 125 config TARGET_SOCFPGA_SOFTING_VINING_FPGA
 126         bool "Softing VIN|ING FPGA (Cyclone V)"
 127         select BOARD_LATE_INIT
 128         select TARGET_SOCFPGA_CYCLONE5
 129
 130 config TARGET_SOCFPGA_SR1500
 131         bool "SR1500 (Cyclone V)"
 132         select TARGET_SOCFPGA_CYCLONE5
 133
 134 config TARGET_SOCFPGA_STRATIX10_SOCDK
 135         bool "Intel SOCFPGA SoCDK (Stratix 10)"
 136         select TARGET_SOCFPGA_STRATIX10
 137
 138 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 139         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 140         select TARGET_SOCFPGA_CYCLONE5
 141
 142 config TARGET_SOCFPGA_TERASIC_DE10_NANO
 143         bool "Terasic DE10-Nano (Cyclone V)"
 144         select TARGET_SOCFPGA_CYCLONE5
 145
 146 config TARGET_SOCFPGA_TERASIC_DE1_SOC
 147         bool "Terasic DE1-SoC (Cyclone V)"
 148         select TARGET_SOCFPGA_CYCLONE5
 149
 150 config TARGET_SOCFPGA_TERASIC_SOCKIT
 151         bool "Terasic SoCkit (Cyclone V)"
 152         select TARGET_SOCFPGA_CYCLONE5
 153
 154 endchoice
 155
 156 config SYS_BOARD
 157         default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
 158         default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 159         default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 160         default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 161         default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 162         default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 163         default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 164         default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 165         default "is1" if TARGET_SOCFPGA_IS1
 166         default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 167         default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
 168         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 169         default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 170         default "sr1500" if TARGET_SOCFPGA_SR1500
 171         default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 172         default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 173
 174 config SYS_VENDOR
 175         default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
 176         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 177         default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 178         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 179         default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
 180         default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
 181         default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 182         default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 183         default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
 184         default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 185         default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 186         default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 187         default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 188         default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 189
 190 config SYS_SOC
 191         default "socfpga"
 192
 193 config SYS_CONFIG_NAME
 194         default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
 195         default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
 196         default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 197         default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 198         default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 199         default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 200         default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 201         default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 202         default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 203         default "socfpga_is1" if TARGET_SOCFPGA_IS1
 204         default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 205         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 206         default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 207         default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 208         default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 209         default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 210
 211 source "board/keymile/Kconfig"
 212
 213 endif