arch/arm/mach-socfpga/Kconfig

   1 if ARCH_SOCFPGA
   2
   3 config ERR_PTR_OFFSET
   4         default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
   5
   6 config NR_DRAM_BANKS
   7         default 1
   8
   9 config SPL_SIZE_LIMIT
  10         default 0x10000 if TARGET_SOCFPGA_GEN5
  11
  12 config SPL_SIZE_LIMIT_PROVIDE_STACK
  13         default 0x200 if TARGET_SOCFPGA_GEN5
  14
  15 config SPL_STACK_R_ADDR
  16         default 0x00800000 if TARGET_SOCFPGA_GEN5
  17
  18 config SPL_SYS_MALLOC_F_LEN
  19         default 0x800 if TARGET_SOCFPGA_GEN5
  20
  21 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
  22         default 0xa2
  23
  24 config SYS_MALLOC_F_LEN
  25         default 0x2000 if TARGET_SOCFPGA_ARRIA10
  26         default 0x2000 if TARGET_SOCFPGA_GEN5
  27
  28 config SYS_TEXT_BASE
  29         default 0x01000040 if TARGET_SOCFPGA_ARRIA10
  30         default 0x01000040 if TARGET_SOCFPGA_GEN5
  31
  32 config TARGET_SOCFPGA_AGILEX
  33         bool
  34         select ARMV8_MULTIENTRY
  35         select ARMV8_SET_SMPEN
  36         select ARMV8_SPIN_TABLE
  37         select CLK
  38         select NCORE_CACHE
  39         select SPL_CLK if SPL
  40
  41 config TARGET_SOCFPGA_ARRIA5
  42         bool
  43         select TARGET_SOCFPGA_GEN5
  44
  45 config TARGET_SOCFPGA_ARRIA10
  46         bool
  47         select SPL_ALTERA_SDRAM
  48         select SPL_BOARD_INIT if SPL
  49         select CLK
  50         select SPL_CLK if SPL
  51         select DM_I2C
  52         select DM_RESET
  53         select SPL_DM_RESET if SPL
  54         select REGMAP
  55         select SPL_REGMAP if SPL
  56         select SYSCON
  57         select SPL_SYSCON if SPL
  58         select ETH_DESIGNWARE_SOCFPGA
  59         imply FPGA_SOCFPGA
  60         imply SPL_USE_TINY_PRINTF
  61
  62 config TARGET_SOCFPGA_CYCLONE5
  63         bool
  64         select TARGET_SOCFPGA_GEN5
  65
  66 config TARGET_SOCFPGA_GEN5
  67         bool
  68         select SPL_ALTERA_SDRAM
  69         imply FPGA_SOCFPGA
  70         imply SPL_SIZE_LIMIT_SUBTRACT_GD
  71         imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
  72         imply SPL_STACK_R
  73         imply SPL_SYS_MALLOC_SIMPLE
  74         imply SPL_USE_TINY_PRINTF
  75
  76 config TARGET_SOCFPGA_STRATIX10
  77         bool
  78         select ARMV8_MULTIENTRY
  79         select ARMV8_SET_SMPEN
  80         select ARMV8_SPIN_TABLE
  81         select FPGA_STRATIX10
  82
  83 choice
  84         prompt "Altera SOCFPGA board select"
  85         optional
  86
  87 config TARGET_SOCFPGA_AGILEX_SOCDK
  88         bool "Intel SOCFPGA SoCDK (Agilex)"
  89         select TARGET_SOCFPGA_AGILEX
  90
  91 config TARGET_SOCFPGA_ARIES_MCVEVK
  92         bool "Aries MCVEVK (Cyclone V)"
  93         select TARGET_SOCFPGA_CYCLONE5
  94
  95 config TARGET_SOCFPGA_ARRIA10_SOCDK
  96         bool "Altera SOCFPGA SoCDK (Arria 10)"
  97         select TARGET_SOCFPGA_ARRIA10
  98
  99 config TARGET_SOCFPGA_ARRIA5_SOCDK
 100         bool "Altera SOCFPGA SoCDK (Arria V)"
 101         select TARGET_SOCFPGA_ARRIA5
 102
 103 config TARGET_SOCFPGA_CYCLONE5_SOCDK
 104         bool "Altera SOCFPGA SoCDK (Cyclone V)"
 105         select TARGET_SOCFPGA_CYCLONE5
 106
 107 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 108         bool "Devboards DBM-SoC1 (Cyclone V)"
 109         select TARGET_SOCFPGA_CYCLONE5
 110
 111 config TARGET_SOCFPGA_EBV_SOCRATES
 112         bool "EBV SoCrates (Cyclone V)"
 113         select TARGET_SOCFPGA_CYCLONE5
 114
 115 config TARGET_SOCFPGA_IS1
 116         bool "IS1 (Cyclone V)"
 117         select TARGET_SOCFPGA_CYCLONE5
 118
 119 config TARGET_SOCFPGA_SOFTING_VINING_FPGA
 120         bool "Softing VIN|ING FPGA (Cyclone V)"
 121         select BOARD_LATE_INIT
 122         select TARGET_SOCFPGA_CYCLONE5
 123
 124 config TARGET_SOCFPGA_SR1500
 125         bool "SR1500 (Cyclone V)"
 126         select TARGET_SOCFPGA_CYCLONE5
 127
 128 config TARGET_SOCFPGA_STRATIX10_SOCDK
 129         bool "Intel SOCFPGA SoCDK (Stratix 10)"
 130         select TARGET_SOCFPGA_STRATIX10
 131
 132 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 133         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 134         select TARGET_SOCFPGA_CYCLONE5
 135
 136 config TARGET_SOCFPGA_TERASIC_DE10_NANO
 137         bool "Terasic DE10-Nano (Cyclone V)"
 138         select TARGET_SOCFPGA_CYCLONE5
 139
 140 config TARGET_SOCFPGA_TERASIC_DE1_SOC
 141         bool "Terasic DE1-SoC (Cyclone V)"
 142         select TARGET_SOCFPGA_CYCLONE5
 143
 144 config TARGET_SOCFPGA_TERASIC_SOCKIT
 145         bool "Terasic SoCkit (Cyclone V)"
 146         select TARGET_SOCFPGA_CYCLONE5
 147
 148 endchoice
 149
 150 config SYS_BOARD
 151         default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
 152         default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 153         default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 154         default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 155         default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 156         default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 157         default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 158         default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 159         default "is1" if TARGET_SOCFPGA_IS1
 160         default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 161         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 162         default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 163         default "sr1500" if TARGET_SOCFPGA_SR1500
 164         default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 165         default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 166
 167 config SYS_VENDOR
 168         default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
 169         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 170         default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 171         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 172         default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
 173         default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
 174         default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 175         default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 176         default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 177         default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 178         default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 179         default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 180         default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 181
 182 config SYS_SOC
 183         default "socfpga"
 184
 185 config SYS_CONFIG_NAME
 186         default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
 187         default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 188         default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 189         default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 190         default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 191         default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 192         default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 193         default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 194         default "socfpga_is1" if TARGET_SOCFPGA_IS1
 195         default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 196         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 197         default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 198         default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 199         default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 200         default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 201
 202 endif