arch/arm/mach-socfpga/Kconfig

   1 if ARCH_SOCFPGA
   2
   3 config ERR_PTR_OFFSET
   4         default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
   5
   6 config NR_DRAM_BANKS
   7         default 1
   8
   9 config SPL_SIZE_LIMIT
  10         default 0x10000 if TARGET_SOCFPGA_GEN5
  11
  12 config SPL_SIZE_LIMIT_PROVIDE_STACK
  13         default 0x200 if TARGET_SOCFPGA_GEN5
  14
  15 config SPL_STACK_R_ADDR
  16         default 0x00800000 if TARGET_SOCFPGA_GEN5
  17
  18 config SPL_SYS_MALLOC_F_LEN
  19         default 0x800 if TARGET_SOCFPGA_GEN5
  20
  21 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
  22         default 0xa2
  23
  24 config SYS_MALLOC_F_LEN
  25         default 0x2000 if TARGET_SOCFPGA_ARRIA10
  26         default 0x2000 if TARGET_SOCFPGA_GEN5
  27
  28 config SYS_TEXT_BASE
  29         default 0x01000040 if TARGET_SOCFPGA_ARRIA10
  30         default 0x01000040 if TARGET_SOCFPGA_GEN5
  31
  32 config TARGET_SOCFPGA_ARRIA5
  33         bool
  34         select TARGET_SOCFPGA_GEN5
  35
  36 config TARGET_SOCFPGA_ARRIA10
  37         bool
  38         select SPL_ALTERA_SDRAM
  39         select SPL_BOARD_INIT if SPL
  40         select CLK
  41         select SPL_CLK if SPL
  42         select DM_I2C
  43         select DM_RESET
  44         select SPL_DM_RESET if SPL
  45         select REGMAP
  46         select SPL_REGMAP if SPL
  47         select SYSCON
  48         select SPL_SYSCON if SPL
  49         select ETH_DESIGNWARE_SOCFPGA
  50         imply FPGA_SOCFPGA
  51         imply SPL_USE_TINY_PRINTF
  52
  53 config TARGET_SOCFPGA_CYCLONE5
  54         bool
  55         select TARGET_SOCFPGA_GEN5
  56
  57 config TARGET_SOCFPGA_GEN5
  58         bool
  59         select SPL_ALTERA_SDRAM
  60         imply FPGA_SOCFPGA
  61         imply SPL_SIZE_LIMIT_SUBTRACT_GD
  62         imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
  63         imply SPL_STACK_R
  64         imply SPL_SYS_MALLOC_SIMPLE
  65         imply SPL_USE_TINY_PRINTF
  66
  67 config TARGET_SOCFPGA_STRATIX10
  68         bool
  69         select ARMV8_MULTIENTRY
  70         select ARMV8_SET_SMPEN
  71         select ARMV8_SPIN_TABLE
  72         select FPGA_STRATIX10
  73
  74 choice
  75         prompt "Altera SOCFPGA board select"
  76         optional
  77
  78 config TARGET_SOCFPGA_ARIES_MCVEVK
  79         bool "Aries MCVEVK (Cyclone V)"
  80         select TARGET_SOCFPGA_CYCLONE5
  81
  82 config TARGET_SOCFPGA_ARRIA10_SOCDK
  83         bool "Altera SOCFPGA SoCDK (Arria 10)"
  84         select TARGET_SOCFPGA_ARRIA10
  85
  86 config TARGET_SOCFPGA_ARRIA5_SOCDK
  87         bool "Altera SOCFPGA SoCDK (Arria V)"
  88         select TARGET_SOCFPGA_ARRIA5
  89
  90 config TARGET_SOCFPGA_CYCLONE5_SOCDK
  91         bool "Altera SOCFPGA SoCDK (Cyclone V)"
  92         select TARGET_SOCFPGA_CYCLONE5
  93
  94 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  95         bool "Devboards DBM-SoC1 (Cyclone V)"
  96         select TARGET_SOCFPGA_CYCLONE5
  97
  98 config TARGET_SOCFPGA_EBV_SOCRATES
  99         bool "EBV SoCrates (Cyclone V)"
 100         select TARGET_SOCFPGA_CYCLONE5
 101
 102 config TARGET_SOCFPGA_IS1
 103         bool "IS1 (Cyclone V)"
 104         select TARGET_SOCFPGA_CYCLONE5
 105
 106 config TARGET_SOCFPGA_SOFTING_VINING_FPGA
 107         bool "Softing VIN|ING FPGA (Cyclone V)"
 108         select BOARD_LATE_INIT
 109         select TARGET_SOCFPGA_CYCLONE5
 110
 111 config TARGET_SOCFPGA_SR1500
 112         bool "SR1500 (Cyclone V)"
 113         select TARGET_SOCFPGA_CYCLONE5
 114
 115 config TARGET_SOCFPGA_STRATIX10_SOCDK
 116         bool "Intel SOCFPGA SoCDK (Stratix 10)"
 117         select TARGET_SOCFPGA_STRATIX10
 118
 119 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 120         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 121         select TARGET_SOCFPGA_CYCLONE5
 122
 123 config TARGET_SOCFPGA_TERASIC_DE10_NANO
 124         bool "Terasic DE10-Nano (Cyclone V)"
 125         select TARGET_SOCFPGA_CYCLONE5
 126
 127 config TARGET_SOCFPGA_TERASIC_DE1_SOC
 128         bool "Terasic DE1-SoC (Cyclone V)"
 129         select TARGET_SOCFPGA_CYCLONE5
 130
 131 config TARGET_SOCFPGA_TERASIC_SOCKIT
 132         bool "Terasic SoCkit (Cyclone V)"
 133         select TARGET_SOCFPGA_CYCLONE5
 134
 135 endchoice
 136
 137 config SYS_BOARD
 138         default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 139         default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 140         default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 141         default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 142         default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 143         default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 144         default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 145         default "is1" if TARGET_SOCFPGA_IS1
 146         default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 147         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 148         default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 149         default "sr1500" if TARGET_SOCFPGA_SR1500
 150         default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 151         default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 152
 153 config SYS_VENDOR
 154         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 155         default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 156         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 157         default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
 158         default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
 159         default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 160         default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 161         default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 162         default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 163         default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 164         default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 165         default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 166
 167 config SYS_SOC
 168         default "socfpga"
 169
 170 config SYS_CONFIG_NAME
 171         default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 172         default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 173         default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 174         default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 175         default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 176         default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 177         default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 178         default "socfpga_is1" if TARGET_SOCFPGA_IS1
 179         default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 180         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 181         default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 182         default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 183         default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 184         default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 185
 186 endif