7 default 65536 if TARGET_SOCFPGA_GEN5
9 config SPL_SIZE_LIMIT_PROVIDE_STACK
10 default 0x200 if TARGET_SOCFPGA_GEN5
12 config SPL_STACK_R_ADDR
13 default 0x00800000 if TARGET_SOCFPGA_GEN5
15 config SPL_SYS_MALLOC_F_LEN
16 default 0x800 if TARGET_SOCFPGA_GEN5
18 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
21 config SYS_MALLOC_F_LEN
22 default 0x2000 if TARGET_SOCFPGA_ARRIA10
23 default 0x2000 if TARGET_SOCFPGA_GEN5
26 default 0x01000040 if TARGET_SOCFPGA_ARRIA10
27 default 0x01000040 if TARGET_SOCFPGA_GEN5
29 config TARGET_SOCFPGA_ARRIA5
31 select TARGET_SOCFPGA_GEN5
33 config TARGET_SOCFPGA_ARRIA10
35 select SPL_ALTERA_SDRAM
36 select SPL_BOARD_INIT if SPL
41 select SPL_DM_RESET if SPL
43 select SPL_REGMAP if SPL
45 select SPL_SYSCON if SPL
46 select ETH_DESIGNWARE_SOCFPGA
50 config TARGET_SOCFPGA_CYCLONE5
52 select TARGET_SOCFPGA_GEN5
54 config TARGET_SOCFPGA_GEN5
56 select SPL_ALTERA_SDRAM
58 imply SPL_SIZE_LIMIT_SUBTRACT_GD
59 imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
61 imply SPL_SYS_MALLOC_SIMPLE
64 config TARGET_SOCFPGA_STRATIX10
66 select ARMV8_MULTIENTRY
67 select ARMV8_SET_SMPEN
68 select ARMV8_SPIN_TABLE
72 prompt "Altera SOCFPGA board select"
75 config TARGET_SOCFPGA_ARIES_MCVEVK
76 bool "Aries MCVEVK (Cyclone V)"
77 select TARGET_SOCFPGA_CYCLONE5
79 config TARGET_SOCFPGA_ARRIA10_SOCDK
80 bool "Altera SOCFPGA SoCDK (Arria 10)"
81 select TARGET_SOCFPGA_ARRIA10
83 config TARGET_SOCFPGA_ARRIA5_SOCDK
84 bool "Altera SOCFPGA SoCDK (Arria V)"
85 select TARGET_SOCFPGA_ARRIA5
87 config TARGET_SOCFPGA_CYCLONE5_SOCDK
88 bool "Altera SOCFPGA SoCDK (Cyclone V)"
89 select TARGET_SOCFPGA_CYCLONE5
91 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
92 bool "Devboards DBM-SoC1 (Cyclone V)"
93 select TARGET_SOCFPGA_CYCLONE5
95 config TARGET_SOCFPGA_EBV_SOCRATES
96 bool "EBV SoCrates (Cyclone V)"
97 select TARGET_SOCFPGA_CYCLONE5
99 config TARGET_SOCFPGA_IS1
100 bool "IS1 (Cyclone V)"
101 select TARGET_SOCFPGA_CYCLONE5
103 config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
104 bool "samtec VIN|ING FPGA (Cyclone V)"
105 select BOARD_LATE_INIT
106 select TARGET_SOCFPGA_CYCLONE5
108 config TARGET_SOCFPGA_SR1500
109 bool "SR1500 (Cyclone V)"
110 select TARGET_SOCFPGA_CYCLONE5
112 config TARGET_SOCFPGA_STRATIX10_SOCDK
113 bool "Intel SOCFPGA SoCDK (Stratix 10)"
114 select TARGET_SOCFPGA_STRATIX10
116 config TARGET_SOCFPGA_TERASIC_DE0_NANO
117 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
118 select TARGET_SOCFPGA_CYCLONE5
120 config TARGET_SOCFPGA_TERASIC_DE10_NANO
121 bool "Terasic DE10-Nano (Cyclone V)"
122 select TARGET_SOCFPGA_CYCLONE5
124 config TARGET_SOCFPGA_TERASIC_DE1_SOC
125 bool "Terasic DE1-SoC (Cyclone V)"
126 select TARGET_SOCFPGA_CYCLONE5
128 config TARGET_SOCFPGA_TERASIC_SOCKIT
129 bool "Terasic SoCkit (Cyclone V)"
130 select TARGET_SOCFPGA_CYCLONE5
135 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
136 default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
137 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
138 default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
139 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
140 default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
141 default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
142 default "is1" if TARGET_SOCFPGA_IS1
143 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
144 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
145 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
146 default "sr1500" if TARGET_SOCFPGA_SR1500
147 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
148 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
151 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
152 default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
153 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
154 default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
155 default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
156 default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
157 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
158 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
159 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
160 default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
161 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
162 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
167 config SYS_CONFIG_NAME
168 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
169 default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
170 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
171 default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
172 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
173 default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
174 default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
175 default "socfpga_is1" if TARGET_SOCFPGA_IS1
176 default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
177 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
178 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
179 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
180 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
181 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA