1 // SPDX-License-Identifier: GPL-2.0+
3 * TLMM driver for Qualcomm APQ8016, APQ8096
5 * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
13 #include <dm/pinctrl.h>
14 #include <linux/bitops.h>
15 #include "pinctrl-snapdragon.h"
17 struct msm_pinctrl_priv {
19 struct msm_pinctrl_data *data;
22 #define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000)
23 #define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
24 #define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
25 #define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
26 #define TLMM_GPIO_DISABLE BIT(9)
28 static const struct pinconf_param msm_conf_params[] = {
29 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 },
30 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
33 static int msm_get_functions_count(struct udevice *dev)
35 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
37 return priv->data->functions_count;
40 static int msm_get_pins_count(struct udevice *dev)
42 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
44 return priv->data->pin_count;
47 static const char *msm_get_function_name(struct udevice *dev,
48 unsigned int selector)
50 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
52 return priv->data->get_function_name(dev, selector);
55 static int msm_pinctrl_probe(struct udevice *dev)
57 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
59 priv->base = devfdt_get_addr(dev);
60 priv->data = (struct msm_pinctrl_data *)dev->driver_data;
62 return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
65 static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
67 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
69 return priv->data->get_pin_name(dev, selector);
72 static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
73 unsigned int func_selector)
75 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
77 clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
78 TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
79 priv->data->get_function_mux(func_selector) << 2);
83 static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
84 unsigned int param, unsigned int argument)
86 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
89 case PIN_CONFIG_DRIVE_STRENGTH:
90 clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
91 TLMM_DRV_STRENGTH_MASK, argument << 6);
93 case PIN_CONFIG_BIAS_DISABLE:
94 clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
104 static struct pinctrl_ops msm_pinctrl_ops = {
105 .get_pins_count = msm_get_pins_count,
106 .get_pin_name = msm_get_pin_name,
107 .set_state = pinctrl_generic_set_state,
108 .pinmux_set = msm_pinmux_set,
109 .pinconf_num_params = ARRAY_SIZE(msm_conf_params),
110 .pinconf_params = msm_conf_params,
111 .pinconf_set = msm_pinconf_set,
112 .get_functions_count = msm_get_functions_count,
113 .get_function_name = msm_get_function_name,
116 static const struct udevice_id msm_pinctrl_ids[] = {
117 { .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data },
118 { .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data },
122 U_BOOT_DRIVER(pinctrl_snapdraon) = {
123 .name = "pinctrl_msm",
124 .id = UCLASS_PINCTRL,
125 .of_match = msm_pinctrl_ids,
126 .priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv),
127 .ops = &msm_pinctrl_ops,
128 .probe = msm_pinctrl_probe,