arch/arm/mach-snapdragon/clock-apq8096.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Clock drivers for Qualcomm APQ8096
   4  *
   5  * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
   6  *
   7  * Based on Little Kernel driver, simplified
   8  */
   9
  10 #include <common.h>
  11 #include <clk-uclass.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <asm/io.h>
  15 #include <linux/bitops.h>
  16 #include "clock-snapdragon.h"
  17
  18 /* GPLL0 clock control registers */
  19 #define GPLL0_STATUS_ACTIVE             BIT(30)
  20 #define APCS_GPLL_ENA_VOTE_GPLL0        BIT(0)
  21
  22 static const struct bcr_regs sdc_regs = {
  23         .cfg_rcgr = SDCC2_CFG_RCGR,
  24         .cmd_rcgr = SDCC2_CMD_RCGR,
  25         .M = SDCC2_M,
  26         .N = SDCC2_N,
  27         .D = SDCC2_D,
  28 };
  29
  30 static const struct pll_vote_clk gpll0_vote_clk = {
  31         .status = GPLL0_STATUS,
  32         .status_bit = GPLL0_STATUS_ACTIVE,
  33         .ena_vote = APCS_GPLL_ENA_VOTE,
  34         .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
  35 };
  36
  37 static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
  38 {
  39         int div = 3;
  40
  41         clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
  42         clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
  43                              CFG_CLK_SRC_GPLL0);
  44         clk_enable_gpll0(priv->base, &gpll0_vote_clk);
  45         clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
  46
  47         return rate;
  48 }
  49
  50 ulong msm_set_rate(struct clk *clk, ulong rate)
  51 {
  52         struct msm_clk_priv *priv = dev_get_priv(clk->dev);
  53
  54         switch (clk->id) {
  55         case 0: /* SDC1 */
  56                 return clk_init_sdc(priv, rate);
  57                 break;
  58         default:
  59                 return 0;
  60         }
  61 }