1 // SPDX-License-Identifier: BSD-3-Clause
3 * Clock drivers for Qualcomm APQ8016
5 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
7 * Based on Little Kernel driver, simplified
11 #include <clk-uclass.h>
15 #include <linux/bitops.h>
16 #include "clock-snapdragon.h"
18 /* GPLL0 clock control registers */
19 #define GPLL0_STATUS_ACTIVE BIT(17)
20 #define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
22 static const struct bcr_regs sdc_regs[] = {
24 .cfg_rcgr = SDCC_CFG_RCGR(1),
25 .cmd_rcgr = SDCC_CMD_RCGR(1),
31 .cfg_rcgr = SDCC_CFG_RCGR(2),
32 .cmd_rcgr = SDCC_CMD_RCGR(2),
39 static struct gpll0_ctrl gpll0_ctrl = {
40 .status = GPLL0_STATUS,
41 .status_bit = GPLL0_STATUS_ACTIVE,
42 .ena_vote = APCS_GPLL_ENA_VOTE,
43 .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
47 static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
49 int div = 8; /* 100MHz default */
51 if (rate == 200000000)
54 clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
55 /* 800Mhz/div, gpll0 */
56 clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
58 clk_enable_gpll0(priv->base, &gpll0_ctrl);
59 clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
64 static const struct bcr_regs uart2_regs = {
65 .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
66 .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
67 .M = BLSP1_UART2_APPS_M,
68 .N = BLSP1_UART2_APPS_N,
69 .D = BLSP1_UART2_APPS_D,
73 static int clk_init_uart(struct msm_clk_priv *priv)
75 /* Enable iface clk */
76 clk_enable_cbc(priv->base + BLSP1_AHB_CBCR);
77 /* 7372800 uart block clock @ GPLL0 */
78 clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
80 clk_enable_gpll0(priv->base, &gpll0_ctrl);
82 clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
87 ulong msm_set_rate(struct clk *clk, ulong rate)
89 struct msm_clk_priv *priv = dev_get_priv(clk->dev);
93 return clk_init_sdc(priv, 0, rate);
96 return clk_init_sdc(priv, 1, rate);
99 return clk_init_uart(priv);