1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
7 #include <debug_uart.h>
15 #include <asm/arch-rockchip/bootrom.h>
17 #include <linux/bitops.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 int board_return_to_bootrom(struct spl_image_info *spl_image,
22 struct spl_boot_device *bootdev)
24 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
29 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
32 const char *board_spl_was_booted_from(void)
34 u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
35 const char *bootdevice_ofpath = NULL;
37 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
38 bootdevice_ofpath = boot_devices[bootdevice_brom_id];
40 if (bootdevice_ofpath)
41 debug("%s: brom_bootdevice_id %x maps to '%s'\n",
42 __func__, bootdevice_brom_id, bootdevice_ofpath);
44 debug("%s: failed to resolve brom_bootdevice_id %x\n",
45 __func__, bootdevice_brom_id);
47 return bootdevice_ofpath;
50 u32 spl_boot_device(void)
52 u32 boot_device = BOOT_DEVICE_MMC1;
54 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
55 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
56 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
57 defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY)
58 return BOOT_DEVICE_SPI;
60 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
61 return BOOT_DEVICE_BOOTROM;
66 u32 spl_mmc_boot_mode(const u32 boot_device)
68 return MMCSD_MODE_RAW;
71 #if !defined(CONFIG_ROCKCHIP_RK3188)
72 #define TIMER_LOAD_COUNT_L 0x00
73 #define TIMER_LOAD_COUNT_H 0x04
74 #define TIMER_CONTROL_REG 0x10
76 #define TIMER_FMODE BIT(0)
77 #define TIMER_RMODE BIT(1)
79 __weak void rockchip_stimer_init(void)
81 /* If Timer already enabled, don't re-init it */
82 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
87 asm volatile("mcr p15, 0, %0, c14, c0, 0"
88 : : "r"(COUNTER_FREQUENCY));
90 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
91 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
92 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
93 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
98 __weak int board_early_init_f(void)
103 __weak int arch_cpu_init(void)
108 void board_init_f(ulong dummy)
112 #ifdef CONFIG_DEBUG_UART
114 * Debug UART can be used from here if required:
119 * printascii("string");
122 debug("\nspl:debug uart enabled in %s\n", __func__);
125 board_early_init_f();
127 ret = spl_early_init();
129 printf("spl_early_init() failed: %d\n", ret);
133 #if !defined(CONFIG_ROCKCHIP_RK3188)
134 rockchip_stimer_init();
136 #ifdef CONFIG_SYS_ARCH_TIMER
137 /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
140 #if !defined(CONFIG_TPL) || defined(CONFIG_SPL_RAM)
141 debug("\nspl:init dram\n");
144 printf("DRAM init failed: %d\n", ret);
147 gd->ram_top = gd->ram_base + get_effective_memsize();
148 gd->ram_top = board_get_usable_ram_top(gd->ram_size);
150 preloader_console_init();
153 #ifdef CONFIG_SPL_LOAD_FIT
154 int __weak board_fit_config_name_match(const char *name)
156 /* Just empty function now - can't decide what to choose */
157 debug("%s: %s\n", __func__, name);