1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
12 #include <asm/arch-rockchip/sdram.h>
13 #include <dm/uclass-internal.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024)
19 struct tos_parameter_t {
37 int dram_init_banksize(void)
39 size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
43 /* Reserve 0x200000 for ATF bl31 */
44 gd->bd->bi_dram[0].start = 0x200000;
45 gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
47 #ifdef CONFIG_SPL_OPTEE
48 struct tos_parameter_t *tos_parameter;
50 tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
51 TRUST_PARAMETER_OFFSET);
53 if (tos_parameter->tee_mem.flags == 1) {
54 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
55 gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
56 - CONFIG_SYS_SDRAM_BASE;
57 gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
58 tos_parameter->tee_mem.size;
59 gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
60 + top - gd->bd->bi_dram[1].start;
62 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
63 gd->bd->bi_dram[0].size = 0x8400000;
64 /* Reserve 32M for OPTEE with TA */
65 gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
66 + gd->bd->bi_dram[0].size + 0x2000000;
67 gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
68 + top - gd->bd->bi_dram[1].start;
71 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
72 gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
79 size_t rockchip_sdram_size(phys_addr_t reg)
81 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
82 size_t chipsize_mb = 0;
88 u32 sys_reg2 = readl(reg);
89 u32 sys_reg3 = readl(reg + 4);
90 u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
91 & SYS_REG_NUM_CH_MASK);
93 dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
94 debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
95 for (ch = 0; ch < ch_num; ch++) {
96 rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
98 cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) &
101 bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
102 if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
103 SYS_REG_VERSION_MASK) == 0x2) {
104 cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
105 SYS_REG_CS1_COL_MASK);
106 if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
107 SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg2 >>
108 SYS_REG_CS0_ROW_SHIFT(ch) &
109 SYS_REG_CS0_ROW_MASK) == 7)
112 cs0_row = 13 + (sys_reg2 >>
113 SYS_REG_CS0_ROW_SHIFT(ch) &
114 SYS_REG_CS0_ROW_MASK) +
116 SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
117 SYS_REG_EXTEND_CS0_ROW_MASK) << 2);
118 if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
119 SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg2 >>
120 SYS_REG_CS1_ROW_SHIFT(ch) &
121 SYS_REG_CS1_ROW_MASK) == 7)
124 cs1_row = 13 + (sys_reg2 >>
125 SYS_REG_CS1_ROW_SHIFT(ch) &
126 SYS_REG_CS1_ROW_MASK) +
128 SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
129 SYS_REG_EXTEND_CS1_ROW_MASK) << 2);
131 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) &
132 SYS_REG_CS0_ROW_MASK);
133 cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) &
134 SYS_REG_CS1_ROW_MASK);
136 bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) &
138 row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
139 SYS_REG_ROW_3_4_MASK;
140 if (dram_type == DDR4) {
141 dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
143 bg = (dbw == 2) ? 2 : 1;
145 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
148 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
149 (cs0_col - cs1_col));
151 chipsize_mb = chipsize_mb * 3 / 4;
152 size_mb += chipsize_mb;
154 debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
155 cs1_row %d bw %d row_3_4 %d\n",
156 rank, cs0_col, cs1_col, bk, cs0_row,
157 cs1_row, bw, row_3_4);
159 debug("rank %d cs0_col %d bk %d cs0_row %d\
161 rank, cs0_col, bk, cs0_row,
166 * This is workaround for issue we can't get correct size for 4GB ram
167 * in 32bit system and available before we really need ram space
168 * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
169 * The size of 4GB is '0x1 00000000', and this value will be truncated
170 * to 0 in 32bit system, and system can not get correct ram size.
171 * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
172 * and we are now setting SDRAM_MAX_SIZE as max available space for
173 * ram in 4GB, so we can use this directly to workaround the issue.
175 * 1. update correct value for SDRAM_MAX_SIZE as what dram
177 * 2. update board_get_usable_ram_top() and dram_init_banksize()
178 * to reserve memory for peripheral space after previous update.
180 if (size_mb > (SDRAM_MAX_SIZE >> 20))
181 size_mb = (SDRAM_MAX_SIZE >> 20);
183 return (size_t)size_mb << 20;
192 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
194 debug("DRAM init failed: %d\n", ret);
197 ret = ram_get_info(dev, &ram);
199 debug("Cannot get DRAM size: %d\n", ret);
202 gd->ram_size = ram.size;
203 debug("SDRAM base=%lx, size=%lx\n",
204 (unsigned long)ram.base, (unsigned long)ram.size);
209 ulong board_get_usable_ram_top(ulong total_size)
211 unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
213 return (gd->ram_top > top) ? top : gd->ram_top;