1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
11 #include <asm/arch-rockchip/sdram.h>
12 #include <dm/uclass-internal.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 #define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024)
18 struct tos_parameter_t {
36 int dram_init_banksize(void)
38 size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
42 /* Reserve 0x200000 for ATF bl31 */
43 gd->bd->bi_dram[0].start = 0x200000;
44 gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
46 #ifdef CONFIG_SPL_OPTEE
47 struct tos_parameter_t *tos_parameter;
49 tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
50 TRUST_PARAMETER_OFFSET);
52 if (tos_parameter->tee_mem.flags == 1) {
53 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
54 gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
55 - CONFIG_SYS_SDRAM_BASE;
56 gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
57 tos_parameter->tee_mem.size;
58 gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
59 + top - gd->bd->bi_dram[1].start;
61 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
62 gd->bd->bi_dram[0].size = 0x8400000;
63 /* Reserve 32M for OPTEE with TA */
64 gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
65 + gd->bd->bi_dram[0].size + 0x2000000;
66 gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
67 + top - gd->bd->bi_dram[1].start;
70 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
71 gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
78 size_t rockchip_sdram_size(phys_addr_t reg)
80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
81 size_t chipsize_mb = 0;
87 u32 sys_reg2 = readl(reg);
88 u32 sys_reg3 = readl(reg + 4);
89 u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
90 & SYS_REG_NUM_CH_MASK);
92 dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
93 debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
94 for (ch = 0; ch < ch_num; ch++) {
95 rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
97 cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) &
100 bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
101 if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
102 SYS_REG_VERSION_MASK) == 0x2) {
103 cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
104 SYS_REG_CS1_COL_MASK);
105 if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
106 SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg2 >>
107 SYS_REG_CS0_ROW_SHIFT(ch) &
108 SYS_REG_CS0_ROW_MASK) == 7)
111 cs0_row = 13 + (sys_reg2 >>
112 SYS_REG_CS0_ROW_SHIFT(ch) &
113 SYS_REG_CS0_ROW_MASK) +
115 SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
116 SYS_REG_EXTEND_CS0_ROW_MASK) << 2);
117 if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
118 SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg2 >>
119 SYS_REG_CS1_ROW_SHIFT(ch) &
120 SYS_REG_CS1_ROW_MASK) == 7)
123 cs1_row = 13 + (sys_reg2 >>
124 SYS_REG_CS1_ROW_SHIFT(ch) &
125 SYS_REG_CS1_ROW_MASK) +
127 SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
128 SYS_REG_EXTEND_CS1_ROW_MASK) << 2);
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) &
131 SYS_REG_CS0_ROW_MASK);
132 cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) &
133 SYS_REG_CS1_ROW_MASK);
135 bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) &
137 row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
138 SYS_REG_ROW_3_4_MASK;
139 if (dram_type == DDR4) {
140 dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
142 bg = (dbw == 2) ? 2 : 1;
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
148 (cs0_col - cs1_col));
150 chipsize_mb = chipsize_mb * 3 / 4;
151 size_mb += chipsize_mb;
153 debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
154 cs1_row %d bw %d row_3_4 %d\n",
155 rank, cs0_col, cs1_col, bk, cs0_row,
156 cs1_row, bw, row_3_4);
158 debug("rank %d cs0_col %d bk %d cs0_row %d\
160 rank, cs0_col, bk, cs0_row,
165 * This is workaround for issue we can't get correct size for 4GB ram
166 * in 32bit system and available before we really need ram space
167 * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
168 * The size of 4GB is '0x1 00000000', and this value will be truncated
169 * to 0 in 32bit system, and system can not get correct ram size.
170 * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
171 * and we are now setting SDRAM_MAX_SIZE as max available space for
172 * ram in 4GB, so we can use this directly to workaround the issue.
174 * 1. update correct value for SDRAM_MAX_SIZE as what dram
176 * 2. update board_get_usable_ram_top() and dram_init_banksize()
177 * to reserve memory for peripheral space after previous update.
179 if (size_mb > (SDRAM_MAX_SIZE >> 20))
180 size_mb = (SDRAM_MAX_SIZE >> 20);
182 return (size_t)size_mb << 20;
191 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
193 debug("DRAM init failed: %d\n", ret);
196 ret = ram_get_info(dev, &ram);
198 debug("Cannot get DRAM size: %d\n", ret);
201 gd->ram_size = ram.size;
202 debug("SDRAM base=%lx, size=%lx\n",
203 (unsigned long)ram.base, (unsigned long)ram.size);
208 ulong board_get_usable_ram_top(ulong total_size)
210 unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
212 return (gd->ram_top > top) ? top : gd->ram_top;