1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
8 #include <asm/arch/bootrom.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/grf_rk3399.h>
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/periph.h>
14 #include <debug_uart.h>
16 #include <dm/pinctrl.h>
21 void board_return_to_bootrom(void)
23 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
26 static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
27 [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
28 [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
29 [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
32 const char *board_spl_was_booted_from(void)
34 u32 bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR);
35 const char *bootdevice_ofpath = NULL;
37 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
38 bootdevice_ofpath = boot_devices[bootdevice_brom_id];
40 if (bootdevice_ofpath)
41 debug("%s: brom_bootdevice_id %x maps to '%s'\n",
42 __func__, bootdevice_brom_id, bootdevice_ofpath);
44 debug("%s: failed to resolve brom_bootdevice_id %x\n",
45 __func__, bootdevice_brom_id);
47 return bootdevice_ofpath;
50 u32 spl_boot_device(void)
52 u32 boot_device = BOOT_DEVICE_MMC1;
54 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
55 return BOOT_DEVICE_BOOTROM;
60 #define TIMER_CHN10_BASE 0xff8680a0
61 #define TIMER_END_COUNT_L 0x00
62 #define TIMER_END_COUNT_H 0x04
63 #define TIMER_INIT_COUNT_L 0x10
64 #define TIMER_INIT_COUNT_H 0x14
65 #define TIMER_CONTROL_REG 0x1c
68 #define TIMER_FMODE (0 << 1)
69 #define TIMER_RMODE (1 << 1)
71 void secure_timer_init(void)
73 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
74 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
75 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
76 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
77 writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
80 void board_debug_uart_init(void)
82 #define GRF_BASE 0xff770000
83 struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
85 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
86 /* Enable early UART0 on the RK3399 */
87 rk_clrsetreg(&grf->gpio2c_iomux,
89 GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
90 rk_clrsetreg(&grf->gpio2c_iomux,
92 GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
94 /* Enable early UART2 channel C on the RK3399 */
95 rk_clrsetreg(&grf->gpio4c_iomux,
97 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
98 rk_clrsetreg(&grf->gpio4c_iomux,
100 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
101 /* Set channel C as UART2 input */
102 rk_clrsetreg(&grf->soc_con7,
103 GRF_UART_DBG_SEL_MASK,
104 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
108 void board_init_f(ulong dummy)
110 struct udevice *pinctrl;
112 struct rk3399_pmusgrf_regs *sgrf;
113 struct rk3399_grf_regs *grf;
119 * Debug UART can be used from here if required:
124 * printascii("string");
127 printascii("U-Boot SPL board init");
130 ret = spl_early_init();
132 debug("spl_early_init() failed: %d\n", ret);
137 * Disable DDR and SRAM security regions.
139 * As we are entered from the BootROM, the region from
140 * 0x0 through 0xfffff (i.e. the first MB of memory) will
141 * be protected. This will cause issues with the DW_MMC
142 * driver, which tries to DMA from/to the stack (likely)
143 * located in this range.
145 sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
146 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
147 rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
149 /* eMMC clock generator: disable the clock multipilier */
150 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
151 rk_clrreg(&grf->emmccore_con[11], 0x0ff);
155 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
157 debug("Pinctrl init failed: %d\n", ret);
161 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
163 debug("DRAM init failed: %d\n", ret);
168 #ifdef CONFIG_SPL_LOAD_FIT
169 int board_fit_config_name_match(const char *name)
171 /* Just empty function now - can't decide what to choose */
172 debug("%s: %s\n", __func__, name);