arch/arm/mach-rockchip/rk3399-board-spl.c

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <debug_uart.h>
   9 #include <dm.h>
  10 #include <ram.h>
  11 #include <spl.h>
  12 #include <asm/gpio.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/periph.h>
  17 #include <asm/arch/sdram.h>
  18 #include <asm/arch/timer.h>
  19 #include <dm/pinctrl.h>
  20 #include <power/regulator.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 u32 spl_boot_device(void)
  25 {
  26         return BOOT_DEVICE_MMC1;
  27 }
  28
  29 u32 spl_boot_mode(const u32 boot_device)
  30 {
  31         return MMCSD_MODE_RAW;
  32 }
  33
  34 #define TIMER_CHN10_BASE        0xff8680a0
  35 #define TIMER_END_COUNT_L       0x00
  36 #define TIMER_END_COUNT_H       0x04
  37 #define TIMER_INIT_COUNT_L      0x10
  38 #define TIMER_INIT_COUNT_H      0x14
  39 #define TIMER_CONTROL_REG       0x1c
  40
  41 #define TIMER_EN        0x1
  42 #define TIMER_FMODE     (0 << 1)
  43 #define TIMER_RMODE     (1 << 1)
  44
  45 void secure_timer_init(void)
  46 {
  47         writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
  48         writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
  49         writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
  50         writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
  51         writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
  52 }
  53
  54 void board_debug_uart_init(void)
  55 {
  56 #include <asm/arch/grf_rk3399.h>
  57 #define GRF_BASE        0xff770000
  58         struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
  59
  60 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
  61         /* Enable early UART0 on the RK3399 */
  62         rk_clrsetreg(&grf->gpio2c_iomux,
  63                      GRF_GPIO2C0_SEL_MASK,
  64                      GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
  65         rk_clrsetreg(&grf->gpio2c_iomux,
  66                      GRF_GPIO2C1_SEL_MASK,
  67                      GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
  68 #else
  69         /* Enable early UART2 channel C on the RK3399 */
  70         rk_clrsetreg(&grf->gpio4c_iomux,
  71                      GRF_GPIO4C3_SEL_MASK,
  72                      GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
  73         rk_clrsetreg(&grf->gpio4c_iomux,
  74                      GRF_GPIO4C4_SEL_MASK,
  75                      GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
  76         /* Set channel C as UART2 input */
  77         rk_clrsetreg(&grf->soc_con7,
  78                      GRF_UART_DBG_SEL_MASK,
  79                      GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
  80 #endif
  81 }
  82
  83 #define GRF_EMMCCORE_CON11 0xff77f02c
  84 #define SGRF_DDR_RGN_CON16 0xff330040
  85 #define SGRF_SLV_SECURE_CON4 0xff33e3d0
  86 void board_init_f(ulong dummy)
  87 {
  88         struct udevice *pinctrl;
  89         struct udevice *dev;
  90         int ret;
  91
  92 #define EARLY_UART
  93 #ifdef EARLY_UART
  94         /*
  95          * Debug UART can be used from here if required:
  96          *
  97          * debug_uart_init();
  98          * printch('a');
  99          * printhex8(0x1234);
 100          * printascii("string");
 101          */
 102         debug_uart_init();
 103         printascii("U-Boot SPL board init");
 104 #endif
 105
 106         /*  Emmc clock generator: disable the clock multipilier */
 107         rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
 108
 109         ret = spl_early_init();
 110         if (ret) {
 111                 debug("spl_early_init() failed: %d\n", ret);
 112                 hang();
 113         }
 114
 115         /*
 116          * Disable DDR and SRAM security regions.
 117          *
 118          * As we are entered from the BootROM, the region from
 119          * 0x0 through 0xfffff (i.e. the first MB of memory) will
 120          * be protected. This will cause issues with the DW_MMC
 121          * driver, which tries to DMA from/to the stack (likely)
 122          * located in this range.
 123          */
 124         rk_clrsetreg(SGRF_DDR_RGN_CON16, 0x1FF, 0);
 125         rk_clrreg(SGRF_SLV_SECURE_CON4, 0x2000);
 126
 127         secure_timer_init();
 128
 129         ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
 130         if (ret) {
 131                 debug("Pinctrl init failed: %d\n", ret);
 132                 return;
 133         }
 134
 135         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 136         if (ret) {
 137                 debug("DRAM init failed: %d\n", ret);
 138                 return;
 139         }
 140 }
 141
 142 void spl_board_init(void)
 143 {
 144         struct udevice *pinctrl;
 145         int ret;
 146
 147         ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
 148         if (ret) {
 149                 debug("%s: Cannot find pinctrl device\n", __func__);
 150                 goto err;
 151         }
 152
 153         /* Enable debug UART */
 154         ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
 155         if (ret) {
 156                 debug("%s: Failed to set up console UART\n", __func__);
 157                 goto err;
 158         }
 159
 160         preloader_console_init();
 161 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 162         back_to_bootrom();
 163 #endif
 164
 165         return;
 166 err:
 167         printf("spl_board_init: Error %d\n", ret);
 168
 169         /* No way to report error here */
 170         hang();
 171 }
 172
 173 #ifdef CONFIG_SPL_LOAD_FIT
 174 int board_fit_config_name_match(const char *name)
 175 {
 176         /* Just empty function now - can't decide what to choose */
 177         debug("%s: %s\n", __func__, name);
 178
 179         return 0;
 180 }
 181 #endif