arch/arm/mach-rockchip/rk3399/rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <spl_gpio.h>
   8 #include <asm/armv8/mmu.h>
   9 #include <asm/io.h>
  10 #include <asm/arch-rockchip/gpio.h>
  11 #include <asm/arch-rockchip/grf_rk3399.h>
  12 #include <asm/arch-rockchip/hardware.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 #define GRF_EMMCCORE_CON11 0xff77f02c
  17 #define GRF_BASE        0xff770000
  18
  19 static struct mm_region rk3399_mem_map[] = {
  20         {
  21                 .virt = 0x0UL,
  22                 .phys = 0x0UL,
  23                 .size = 0xf8000000UL,
  24                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  25                          PTE_BLOCK_INNER_SHARE
  26         }, {
  27                 .virt = 0xf8000000UL,
  28                 .phys = 0xf8000000UL,
  29                 .size = 0x08000000UL,
  30                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  31                          PTE_BLOCK_NON_SHARE |
  32                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  33         }, {
  34                 /* List terminator */
  35                 0,
  36         }
  37 };
  38
  39 struct mm_region *mem_map = rk3399_mem_map;
  40
  41 int dram_init_banksize(void)
  42 {
  43         size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
  44
  45         /* Reserve 0x200000 for ATF bl31 */
  46         gd->bd->bi_dram[0].start = 0x200000;
  47         gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
  48
  49         return 0;
  50 }
  51
  52 int arch_cpu_init(void)
  53 {
  54         /* We do some SoC one time setting here. */
  55         struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
  56
  57         /* Emmc clock generator: disable the clock multipilier */
  58         rk_clrreg(&grf->emmccore_con[11], 0x0ff);
  59
  60         return 0;
  61 }
  62
  63 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  64 void board_debug_uart_init(void)
  65 {
  66 #define GRF_BASE        0xff770000
  67 #define GPIO0_BASE      0xff720000
  68 #define PMUGRF_BASE     0xff320000
  69         struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
  70 #ifdef CONFIG_TARGET_CHROMEBOOK_BOB
  71         struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
  72         struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
  73 #endif
  74
  75 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
  76         /* Enable early UART0 on the RK3399 */
  77         rk_clrsetreg(&grf->gpio2c_iomux,
  78                      GRF_GPIO2C0_SEL_MASK,
  79                      GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
  80         rk_clrsetreg(&grf->gpio2c_iomux,
  81                      GRF_GPIO2C1_SEL_MASK,
  82                      GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
  83 #else
  84 # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
  85         rk_setreg(&grf->io_vsel, 1 << 0);
  86
  87         /*
  88          * Let's enable these power rails here, we are already running the SPI
  89          * Flash based code.
  90          */
  91         spl_gpio_output(gpio, GPIO(BANK_B, 2), 1);  /* PP1500_EN */
  92         spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
  93
  94         spl_gpio_output(gpio, GPIO(BANK_B, 4), 1);  /* PP3000_EN */
  95         spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
  96 #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
  97
  98         /* Enable early UART2 channel C on the RK3399 */
  99         rk_clrsetreg(&grf->gpio4c_iomux,
 100                      GRF_GPIO4C3_SEL_MASK,
 101                      GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
 102         rk_clrsetreg(&grf->gpio4c_iomux,
 103                      GRF_GPIO4C4_SEL_MASK,
 104                      GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
 105         /* Set channel C as UART2 input */
 106         rk_clrsetreg(&grf->soc_con7,
 107                      GRF_UART_DBG_SEL_MASK,
 108                      GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
 109 #endif
 110 }
 111 #endif