1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
8 #include <asm/armv8/mmu.h>
10 #include <asm/arch-rockchip/gpio.h>
11 #include <asm/arch-rockchip/grf_rk3399.h>
12 #include <asm/arch-rockchip/hardware.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 #define GRF_EMMCCORE_CON11 0xff77f02c
17 #define GRF_BASE 0xff770000
19 static struct mm_region rk3399_mem_map[] = {
24 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
30 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
32 PTE_BLOCK_PXN | PTE_BLOCK_UXN
39 struct mm_region *mem_map = rk3399_mem_map;
41 int dram_init_banksize(void)
43 size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
45 /* Reserve 0x200000 for ATF bl31 */
46 gd->bd->bi_dram[0].start = 0x200000;
47 gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
52 int arch_cpu_init(void)
54 /* We do some SoC one time setting here. */
55 struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
57 /* Emmc clock generator: disable the clock multipilier */
58 rk_clrreg(&grf->emmccore_con[11], 0x0ff);
63 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
64 void board_debug_uart_init(void)
66 #define GRF_BASE 0xff770000
67 #define GPIO0_BASE 0xff720000
68 #define PMUGRF_BASE 0xff320000
69 struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
70 #ifdef CONFIG_TARGET_CHROMEBOOK_BOB
71 struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
72 struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
75 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
76 /* Enable early UART0 on the RK3399 */
77 rk_clrsetreg(&grf->gpio2c_iomux,
79 GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
80 rk_clrsetreg(&grf->gpio2c_iomux,
82 GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
83 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
84 /* Enable early UART3 on the RK3399 */
85 rk_clrsetreg(&grf->gpio3b_iomux,
87 GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
88 rk_clrsetreg(&grf->gpio3b_iomux,
90 GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
92 # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
93 rk_setreg(&grf->io_vsel, 1 << 0);
96 * Let's enable these power rails here, we are already running the SPI
99 spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
100 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
102 spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
103 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
104 #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
106 /* Enable early UART2 channel C on the RK3399 */
107 rk_clrsetreg(&grf->gpio4c_iomux,
108 GRF_GPIO4C3_SEL_MASK,
109 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
110 rk_clrsetreg(&grf->gpio4c_iomux,
111 GRF_GPIO4C4_SEL_MASK,
112 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
113 /* Set channel C as UART2 input */
114 rk_clrsetreg(&grf->soc_con7,
115 GRF_UART_DBG_SEL_MASK,
116 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);