1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
10 #include <asm/armv8/mmu.h>
12 #include <asm/arch-rockchip/bootrom.h>
13 #include <asm/arch-rockchip/clock.h>
14 #include <asm/arch-rockchip/gpio.h>
15 #include <asm/arch-rockchip/grf_rk3399.h>
16 #include <asm/arch-rockchip/hardware.h>
17 #include <power/regulator.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 #define GRF_EMMCCORE_CON11 0xff77f02c
22 #define GRF_BASE 0xff770000
24 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
25 [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
26 [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
27 [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
30 static struct mm_region rk3399_mem_map[] = {
35 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
41 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
43 PTE_BLOCK_PXN | PTE_BLOCK_UXN
50 struct mm_region *mem_map = rk3399_mem_map;
52 #ifdef CONFIG_SPL_BUILD
54 #define TIMER_END_COUNT_L 0x00
55 #define TIMER_END_COUNT_H 0x04
56 #define TIMER_INIT_COUNT_L 0x10
57 #define TIMER_INIT_COUNT_H 0x14
58 #define TIMER_CONTROL_REG 0x1c
61 #define TIMER_FMODE BIT(0)
62 #define TIMER_RMODE BIT(1)
64 void rockchip_stimer_init(void)
66 /* If Timer already enabled, don't re-init it */
67 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
72 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L);
73 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H);
74 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L);
75 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H);
76 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \
81 int dram_init_banksize(void)
83 size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
85 /* Reserve 0x200000 for ATF bl31 */
86 gd->bd->bi_dram[0].start = 0x200000;
87 gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
92 int arch_cpu_init(void)
95 #ifdef CONFIG_SPL_BUILD
96 struct rk3399_pmusgrf_regs *sgrf;
97 struct rk3399_grf_regs *grf;
100 * Disable DDR and SRAM security regions.
102 * As we are entered from the BootROM, the region from
103 * 0x0 through 0xfffff (i.e. the first MB of memory) will
104 * be protected. This will cause issues with the DW_MMC
105 * driver, which tries to DMA from/to the stack (likely)
106 * located in this range.
108 sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
109 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
110 rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
112 /* eMMC clock generator: disable the clock multipilier */
113 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
114 rk_clrreg(&grf->emmccore_con[11], 0x0ff);
120 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
121 void board_debug_uart_init(void)
123 #define GRF_BASE 0xff770000
124 #define GPIO0_BASE 0xff720000
125 #define PMUGRF_BASE 0xff320000
126 struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
127 #ifdef CONFIG_TARGET_CHROMEBOOK_BOB
128 struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
129 struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
132 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
133 /* Enable early UART0 on the RK3399 */
134 rk_clrsetreg(&grf->gpio2c_iomux,
135 GRF_GPIO2C0_SEL_MASK,
136 GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
137 rk_clrsetreg(&grf->gpio2c_iomux,
138 GRF_GPIO2C1_SEL_MASK,
139 GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
140 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
141 /* Enable early UART3 on the RK3399 */
142 rk_clrsetreg(&grf->gpio3b_iomux,
143 GRF_GPIO3B6_SEL_MASK,
144 GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
145 rk_clrsetreg(&grf->gpio3b_iomux,
146 GRF_GPIO3B7_SEL_MASK,
147 GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
149 # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
150 rk_setreg(&grf->io_vsel, 1 << 0);
153 * Let's enable these power rails here, we are already running the SPI
156 spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
157 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
159 spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
160 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
161 #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
163 /* Enable early UART2 channel C on the RK3399 */
164 rk_clrsetreg(&grf->gpio4c_iomux,
165 GRF_GPIO4C3_SEL_MASK,
166 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
167 rk_clrsetreg(&grf->gpio4c_iomux,
168 GRF_GPIO4C4_SEL_MASK,
169 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
170 /* Set channel C as UART2 input */
171 rk_clrsetreg(&grf->soc_con7,
172 GRF_UART_DBG_SEL_MASK,
173 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
178 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
179 const char *spl_decode_boot_device(u32 boot_device)
182 static const struct {
185 } spl_boot_devices_tbl[] = {
186 { BOOT_DEVICE_MMC1, "/dwmmc@fe320000" },
187 { BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
188 { BOOT_DEVICE_SPI, "/spi@ff1d0000" },
191 for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
192 if (spl_boot_devices_tbl[i].boot_device == boot_device)
193 return spl_boot_devices_tbl[i].ofpath;
198 void spl_perform_fixups(struct spl_image_info *spl_image)
200 void *blob = spl_image->fdt_addr;
201 const char *boot_ofpath;
205 * Inject the ofpath of the device the full U-Boot (or Linux in
206 * Falcon-mode) was booted from into the FDT, if a FDT has been
207 * loaded at the same time.
212 boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
214 pr_err("%s: could not map boot_device to ofpath\n", __func__);
218 chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
220 pr_err("%s: could not find/create '/chosen'\n", __func__);
223 fdt_setprop_string(blob, chosen,
224 "u-boot,spl-boot-device", boot_ofpath);
227 #if defined(SPL_GPIO_SUPPORT)
228 static void rk3399_force_power_on_reset(void)
231 struct gpio_desc sysreset_gpio;
233 debug("%s: trying to force a power-on reset\n", __func__);
235 node = ofnode_path("/config");
236 if (!ofnode_valid(node)) {
237 debug("%s: no /config node?\n", __func__);
241 if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
242 &sysreset_gpio, GPIOD_IS_OUT)) {
243 debug("%s: could not find a /config/sysreset-gpio\n", __func__);
247 dm_gpio_set_value(&sysreset_gpio, 1);
251 void spl_board_init(void)
253 #if defined(SPL_GPIO_SUPPORT)
254 struct rk3399_cru *cru = rockchip_get_cru();
257 * The RK3399 resets only 'almost all logic' (see also in the TRM
258 * "3.9.4 Global software reset"), when issuing a software reset.
259 * This may cause issues during boot-up for some configurations of
260 * the application software stack.
262 * To work around this, we test whether the last reset reason was
263 * a power-on reset and (if not) issue an overtemp-reset to reset
266 * While this was previously fixed by modifying the various places
267 * that could generate a software reset (e.g. U-Boot's sysreset
268 * driver, the ATF or Linux), we now have it here to ensure that
269 * we no longer have to track this through the various components.
271 if (cru->glb_rst_st != 0)
272 rk3399_force_power_on_reset();
275 #if defined(SPL_DM_REGULATOR)
277 * Turning the eMMC and SPI back on (if disabled via the Qseven
278 * BIOS_ENABLE) signal is done through a always-on regulator).
280 if (regulators_enable_boot_on(false))
281 debug("%s: Cannot enable boot on regulator\n", __func__);