arch/arm/mach-rockchip/rk3328/rk3328.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <asm/arch-rockchip/bootrom.h>
   8 #include <asm/arch-rockchip/hardware.h>
   9 #include <asm/arch-rockchip/grf_rk3328.h>
  10 #include <asm/arch-rockchip/uart.h>
  11 #include <asm/armv8/mmu.h>
  12 #include <asm/io.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 #define CRU_BASE                0xFF440000
  17 #define GRF_BASE                0xFF100000
  18 #define UART2_BASE              0xFF130000
  19
  20 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  21         [BROM_BOOTSOURCE_EMMC] = "rksdmmc@ff520000",
  22         [BROM_BOOTSOURCE_SD] = "rksdmmc@ff500000",
  23 };
  24
  25 static struct mm_region rk3328_mem_map[] = {
  26         {
  27                 .virt = 0x0UL,
  28                 .phys = 0x0UL,
  29                 .size = 0xff000000UL,
  30                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  31                          PTE_BLOCK_INNER_SHARE
  32         }, {
  33                 .virt = 0xff000000UL,
  34                 .phys = 0xff000000UL,
  35                 .size = 0x1000000UL,
  36                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  37                          PTE_BLOCK_NON_SHARE |
  38                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  39         }, {
  40                 /* List terminator */
  41                 0,
  42         }
  43 };
  44
  45 struct mm_region *mem_map = rk3328_mem_map;
  46
  47 int arch_cpu_init(void)
  48 {
  49         /* We do some SoC one time setting here. */
  50
  51         return 0;
  52 }
  53
  54 void board_debug_uart_init(void)
  55 {
  56         struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
  57         struct rk_uart * const uart = (void *)UART2_BASE;
  58         enum{
  59                 GPIO2A0_SEL_SHIFT       = 0,
  60                 GPIO2A0_SEL_MASK        = 3 << GPIO2A0_SEL_SHIFT,
  61                 GPIO2A0_UART2_TX_M1     = 1,
  62
  63                 GPIO2A1_SEL_SHIFT       = 2,
  64                 GPIO2A1_SEL_MASK        = 3 << GPIO2A1_SEL_SHIFT,
  65                 GPIO2A1_UART2_RX_M1     = 1,
  66         };
  67         enum {
  68                 IOMUX_SEL_UART2_SHIFT   = 0,
  69                 IOMUX_SEL_UART2_MASK    = 3 << IOMUX_SEL_UART2_SHIFT,
  70                 IOMUX_SEL_UART2_M0      = 0,
  71                 IOMUX_SEL_UART2_M1,
  72         };
  73
  74         /* uart_sel_clk default select 24MHz */
  75         writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148);
  76
  77         /* init uart baud rate 1500000 */
  78         writel(0x83, &uart->lcr);
  79         writel(0x1, &uart->rbr);
  80         writel(0x3, &uart->lcr);
  81
  82         /* Enable early UART2 */
  83         rk_clrsetreg(&grf->com_iomux,
  84                      IOMUX_SEL_UART2_MASK,
  85                      IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT);
  86         rk_clrsetreg(&grf->gpio2a_iomux,
  87                      GPIO2A0_SEL_MASK,
  88                      GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT);
  89         rk_clrsetreg(&grf->gpio2a_iomux,
  90                      GPIO2A1_SEL_MASK,
  91                      GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
  92
  93         /* enable FIFO */
  94         writel(0x1, &uart->sfe);
  95 }