1 // SPDX-License-Identifier: GPL-2.0+
3 *Copyright (c) 2018 Rockchip Electronics Co., Ltd
7 #include <asm/arch/grf_rk3308.h>
8 #include <asm/arch-rockchip/hardware.h>
10 #include <debug_uart.h>
12 DECLARE_GLOBAL_DATA_PTR;
14 #include <asm/armv8/mmu.h>
15 static struct mm_region rk3308_mem_map[] = {
20 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
26 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
28 PTE_BLOCK_PXN | PTE_BLOCK_UXN
35 struct mm_region *mem_map = rk3308_mem_map;
37 #define GRF_BASE 0xff000000
38 #define SGRF_BASE 0xff2b0000
42 GPIO1C7_MASK = GENMASK(11, 8),
50 GPIO1C6_MASK = GENMASK(7, 4),
58 GPIO4D3_MASK = GENMASK(7, 6),
64 GPIO4D2_MASK = GENMASK(5, 4),
69 UART2_IO_SEL_SHIFT = 2,
70 UART2_IO_SEL_MASK = GENMASK(3, 2),
75 GPIO3B3_SEL_SRC_CTRL_SHIFT = 7,
76 GPIO3B3_SEL_SRC_CTRL_MASK = BIT(7),
77 GPIO3B3_SEL_SRC_CTRL_IOMUX = 0,
78 GPIO3B3_SEL_SRC_CTRL_SEL_PLUS,
80 GPIO3B3_SEL_PLUS_SHIFT = 4,
81 GPIO3B3_SEL_PLUS_MASK = GENMASK(6, 4),
82 GPIO3B3_SEL_PLUS_GPIO3_B3 = 0,
83 GPIO3B3_SEL_PLUS_FLASH_ALE,
84 GPIO3B3_SEL_PLUS_EMMC_PWREN,
85 GPIO3B3_SEL_PLUS_SPI1_CLK,
86 GPIO3B3_SEL_PLUS_LCDC_D23_M1,
88 GPIO3B2_SEL_SRC_CTRL_SHIFT = 3,
89 GPIO3B2_SEL_SRC_CTRL_MASK = BIT(3),
90 GPIO3B2_SEL_SRC_CTRL_IOMUX = 0,
91 GPIO3B2_SEL_SRC_CTRL_SEL_PLUS,
93 GPIO3B2_SEL_PLUS_SHIFT = 0,
94 GPIO3B2_SEL_PLUS_MASK = GENMASK(2, 0),
95 GPIO3B2_SEL_PLUS_GPIO3_B2 = 0,
96 GPIO3B2_SEL_PLUS_FLASH_RDN,
97 GPIO3B2_SEL_PLUS_EMMC_RSTN,
98 GPIO3B2_SEL_PLUS_SPI1_MISO,
99 GPIO3B2_SEL_PLUS_LCDC_D22_M1,
103 IOVSEL3_CTRL_SHIFT = 8,
104 IOVSEL3_CTRL_MASK = BIT(8),
105 VCCIO3_SEL_BY_GPIO = 0,
106 VCCIO3_SEL_BY_IOVSEL3,
109 IOVSEL3_MASK = BIT(3),
115 * The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc
116 * interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults
117 * use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware,
118 * then we can switch to io_vsel3 after system power on, and release GPIO0_A4
124 int rk_board_init(void)
126 static struct rk3308_grf * const grf = (void *)GRF_BASE;
130 ret = gpio_request(GPIO0_A4, "gpio0_a4");
132 printf("request for gpio0_a4 failed:%d\n", ret);
136 gpio_direction_input(GPIO0_A4);
138 if (gpio_get_value(GPIO0_A4))
139 val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
140 VCCIO3_1V8 << IOVSEL3_SHIFT;
142 val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
143 VCCIO3_3V3 << IOVSEL3_SHIFT;
144 rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val);
150 #if defined(CONFIG_DEBUG_UART)
151 __weak void board_debug_uart_init(void)
153 static struct rk3308_grf * const grf = (void *)GRF_BASE;
155 /* Enable early UART2 channel m1 on the rk3308 */
156 rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
157 UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
158 rk_clrsetreg(&grf->gpio4d_iomux,
159 GPIO4D3_MASK | GPIO4D2_MASK,
160 GPIO4D2_UART2_RX_M1 << GPIO4D2_SHIFT |
161 GPIO4D3_UART2_TX_M1 << GPIO4D3_SHIFT);
165 #if defined(CONFIG_SPL_BUILD)
166 int arch_cpu_init(void)
168 static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE;
170 /* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */
171 rk_clrreg(&sgrf->con_secure0, 0x2b83);