arch/arm/mach-rockchip/rk3308/rk3308.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *Copyright (c) 2018 Rockchip Electronics Co., Ltd
   4  */
   5 #include <common.h>
   6 #include <asm/io.h>
   7 #include <asm/arch/grf_rk3308.h>
   8 #include <asm/arch-rockchip/hardware.h>
   9 #include <asm/gpio.h>
  10 #include <debug_uart.h>
  11
  12 DECLARE_GLOBAL_DATA_PTR;
  13
  14 #include <asm/armv8/mmu.h>
  15 static struct mm_region rk3308_mem_map[] = {
  16         {
  17                 .virt = 0x0UL,
  18                 .phys = 0x0UL,
  19                 .size = 0xff000000UL,
  20                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  21                          PTE_BLOCK_INNER_SHARE
  22         }, {
  23                 .virt = 0xff000000UL,
  24                 .phys = 0xff000000UL,
  25                 .size = 0x01000000UL,
  26                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  27                          PTE_BLOCK_NON_SHARE |
  28                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  29         }, {
  30                 /* List terminator */
  31                 0,
  32         }
  33 };
  34
  35 struct mm_region *mem_map = rk3308_mem_map;
  36
  37 #define GRF_BASE        0xff000000
  38 #define SGRF_BASE       0xff2b0000
  39
  40 enum {
  41         GPIO1C7_SHIFT           = 8,
  42         GPIO1C7_MASK            = GENMASK(11, 8),
  43         GPIO1C7_GPIO            = 0,
  44         GPIO1C7_UART1_RTSN,
  45         GPIO1C7_UART2_TX_M0,
  46         GPIO1C7_SPI2_MOSI,
  47         GPIO1C7_JTAG_TMS,
  48
  49         GPIO1C6_SHIFT           = 4,
  50         GPIO1C6_MASK            = GENMASK(7, 4),
  51         GPIO1C6_GPIO            = 0,
  52         GPIO1C6_UART1_CTSN,
  53         GPIO1C6_UART2_RX_M0,
  54         GPIO1C6_SPI2_MISO,
  55         GPIO1C6_JTAG_TCLK,
  56
  57         GPIO4D3_SHIFT           = 6,
  58         GPIO4D3_MASK            = GENMASK(7, 6),
  59         GPIO4D3_GPIO            = 0,
  60         GPIO4D3_SDMMC_D3,
  61         GPIO4D3_UART2_TX_M1,
  62
  63         GPIO4D2_SHIFT           = 4,
  64         GPIO4D2_MASK            = GENMASK(5, 4),
  65         GPIO4D2_GPIO            = 0,
  66         GPIO4D2_SDMMC_D2,
  67         GPIO4D2_UART2_RX_M1,
  68
  69         UART2_IO_SEL_SHIFT      = 2,
  70         UART2_IO_SEL_MASK       = GENMASK(3, 2),
  71         UART2_IO_SEL_M0         = 0,
  72         UART2_IO_SEL_M1,
  73         UART2_IO_SEL_USB,
  74
  75         GPIO3B3_SEL_SRC_CTRL_SHIFT      = 7,
  76         GPIO3B3_SEL_SRC_CTRL_MASK       = BIT(7),
  77         GPIO3B3_SEL_SRC_CTRL_IOMUX      = 0,
  78         GPIO3B3_SEL_SRC_CTRL_SEL_PLUS,
  79
  80         GPIO3B3_SEL_PLUS_SHIFT          = 4,
  81         GPIO3B3_SEL_PLUS_MASK           = GENMASK(6, 4),
  82         GPIO3B3_SEL_PLUS_GPIO3_B3       = 0,
  83         GPIO3B3_SEL_PLUS_FLASH_ALE,
  84         GPIO3B3_SEL_PLUS_EMMC_PWREN,
  85         GPIO3B3_SEL_PLUS_SPI1_CLK,
  86         GPIO3B3_SEL_PLUS_LCDC_D23_M1,
  87
  88         GPIO3B2_SEL_SRC_CTRL_SHIFT      = 3,
  89         GPIO3B2_SEL_SRC_CTRL_MASK       = BIT(3),
  90         GPIO3B2_SEL_SRC_CTRL_IOMUX      = 0,
  91         GPIO3B2_SEL_SRC_CTRL_SEL_PLUS,
  92
  93         GPIO3B2_SEL_PLUS_SHIFT          = 0,
  94         GPIO3B2_SEL_PLUS_MASK           = GENMASK(2, 0),
  95         GPIO3B2_SEL_PLUS_GPIO3_B2       = 0,
  96         GPIO3B2_SEL_PLUS_FLASH_RDN,
  97         GPIO3B2_SEL_PLUS_EMMC_RSTN,
  98         GPIO3B2_SEL_PLUS_SPI1_MISO,
  99         GPIO3B2_SEL_PLUS_LCDC_D22_M1,
 100 };
 101
 102 enum {
 103         IOVSEL3_CTRL_SHIFT      = 8,
 104         IOVSEL3_CTRL_MASK       = BIT(8),
 105         VCCIO3_SEL_BY_GPIO      = 0,
 106         VCCIO3_SEL_BY_IOVSEL3,
 107
 108         IOVSEL3_SHIFT           = 3,
 109         IOVSEL3_MASK            = BIT(3),
 110         VCCIO3_3V3              = 0,
 111         VCCIO3_1V8,
 112 };
 113
 114 /*
 115  * The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc
 116  * interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults
 117  * use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware,
 118  * then we can switch to io_vsel3 after system power on, and release GPIO0_A4
 119  * for other usage.
 120  */
 121
 122 #define GPIO0_A4        4
 123
 124 int rk_board_init(void)
 125 {
 126         static struct rk3308_grf * const grf = (void *)GRF_BASE;
 127         u32 val;
 128         int ret;
 129
 130         ret = gpio_request(GPIO0_A4, "gpio0_a4");
 131         if (ret < 0) {
 132                 printf("request for gpio0_a4 failed:%d\n", ret);
 133                 return 0;
 134         }
 135
 136         gpio_direction_input(GPIO0_A4);
 137
 138         if (gpio_get_value(GPIO0_A4))
 139                 val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
 140                       VCCIO3_1V8 << IOVSEL3_SHIFT;
 141         else
 142                 val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
 143                       VCCIO3_3V3 << IOVSEL3_SHIFT;
 144         rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val);
 145
 146         gpio_free(GPIO0_A4);
 147         return 0;
 148 }
 149
 150 #if defined(CONFIG_DEBUG_UART)
 151 __weak void board_debug_uart_init(void)
 152 {
 153         static struct rk3308_grf * const grf = (void *)GRF_BASE;
 154
 155         /* Enable early UART2 channel m1 on the rk3308 */
 156         rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
 157                      UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
 158         rk_clrsetreg(&grf->gpio4d_iomux,
 159                      GPIO4D3_MASK | GPIO4D2_MASK,
 160                      GPIO4D2_UART2_RX_M1 << GPIO4D2_SHIFT |
 161                      GPIO4D3_UART2_TX_M1 << GPIO4D3_SHIFT);
 162 }
 163 #endif
 164
 165 #if defined(CONFIG_SPL_BUILD)
 166 int arch_cpu_init(void)
 167 {
 168         static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE;
 169
 170         /* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */
 171         rk_clrreg(&sgrf->con_secure0, 0x2b83);
 172
 173         return 0;
 174 }
 175 #endif